Session #1: Designing-In Reliability (DIR), Chairs: John Suehle, NIST &
Brian Langley, Agilent Technologies
- DIR-1
- "Deep-Censoring Method For Early Reliability Assessment", H.A.
Schafft, NIST, L.M. Head, Rowan Univ., J.A. Lechner, Consultant, J.P.
Gill, & T.D. Sullivan, IBM
- DIR-2
- "Analysis & Optimization of Stress Conditions for Gate Oxide
Wearout Using Monte Carlo Simulation", R.P. Vollertsen, Infineon
Technologies, & A. Strong, IBM
- DIR-3
- "Design Rule Limitations Due to Hot Carrier Degradation of NMOS
Transistor Under DC Stress", D. Regis, C. Dekeukeleire, W.
Vanderbauwhede, A. Demesmaeker, & A. Pergoot, Alcatel Microelectronics
- DIR-4
- withdrawn
Session #2 Customer Product Reliability Requirements (CPR), Chairs: Bill
Vigrass, TI & Cleston Messick, National Semiconductor
- CPR-1
- "On the Methodology of Assessing Hot-Carrier Reliability of Analog
Circuits", H. Le, MIT, W. Jiang, Intel, J.E. Chung, Motorola, P.J.
Marcoux, Hewlett Packard
- CPR-2
- "Fast-bit-limited Lifetime Modeling of Advanced Floating Gate
Non-volatile Memories", A. Scarpa, G. Tao, H. Dijkstra &
F. Kuper, Philips Semiconductors
- CPR-3
- "Reliability Studies on Sub 100 nm SOI-MNSFETs", S. Mahapatra,
V.R. Rao, J. Vasi, Indian Institute of Technology, B. Cheng, Motorola,
& J.C.S. Woo, Univ. of CA, Los Angeles
- CPR-4
- "Fault-Tolerant Approaches Based on Evolvable Hardware & Using
Reconfigurable Electronic Devices", D. Keymeulen, A. Stoica, R.
Zebulum & Y. Jin, JPL
Session #3 Contributors to Failure (CTF), Chairs: Andreas Martin, Infineon
Technologies & Nguyen Bui, Parthus Technologies
- CTF-1
- "Plasma-Induced-Damage (PID) Free 29Å Nitrided Gate Oxide of
130 nm CMOS Devices for High Performance Microprocessor Manufacturing", G.
Klein, H. Nariman, D. Wu, J. Tao, B. Bandyopadhyay, D. Wristers, E. Ibok,
M. McBride, J. Tsiang, D.H. Ju, and P. Fang, AMD
- CTF-2
- "Quasi-Breakdown in Ultra-thin Oxides: Some Insights on the Physical
Mechanisms", S. Bruyere, D. Roy, E. Vincent, STMicroelectronics, & G.
Ghibaudo, LPCS/ENSERG
- CTF-3
- "Soft Breakdown Model of 20 Å Gate Oxide", C.-Y. Ko, R.Y.
Shiue, & J. Yue, TSMC
- CTF-4
- "Gate Reliability Comparison of 110 & 100 Substrates", A.
Strong, E. Wu, IBM, H. Tews, Infineon Technologies, D. Tibel, IBM, R.
Malik, Infineon Technologies, & O. Cain, CDI Corp.
Session #4: Reliability Characterisation & Models (RCM), Chairs: Harry
A. Schafft, NIST & Murat Okandan, Sandia National Labs
- RCM-1
- "Electromigration Testing on Via Line Structures with a SWEAT Method
in Comparision to Standard Package Level Tests", A. Zitzelsberger, A.
Pietsch, & J. von Hagen, Infineon Technologies
- RCM-2
- "Comparison of Isothermal, Constant Current & SWEAT Wafer Level
EM Testing Methods", D. Tibel, T. Lee, & T. Sullivan, IBM
Microelectronics
- RCM-3
- "A Correlation Between Highly Accelerated Wafer Level & Standard
Package Level Electromigration Tests on Deep Sub-micron via-line
Structures", M. Lepper, R. Bauer, & A.E. Zitzelsberger, Infineon
Technologies
- RCM-4
- "The Effect of Stress Interruption & Alternating Biased Stress on
Ultra-Thin Gate Dielectric Reliability", B. Wang, Univ. of MD, J.S.
Suehle, E.M. Vogel, NIST, & J.B. Bernstein, Univ. of MD
Session #5 Wafer Level Reliability (WLR), Chairs: Emmanuel Vincent,
STMicroelectronics & Tomasz Brozek, PDF Solutions
- WLR-1
- "Basic BEOL Parameters from Isothermal Wafer Level Electromigration
Testing", T.D. Sullivan, T. Lee & D. Tibel, IBM Microelectronics
- WLR-2
- "New SWEAT Method for Fast, Accurate & Stable Electromigration
Testing on Wafer Level", J. von Hagen, G. Antonin, J. Fazekas,
Infineon Technologies, L.M. Head, Rowan Univ., & H.A. Schafft, NIST
- WLR-3
- "A Novel Electrical Test to Differentiate Gate-to-Source/Drain
Silicide Short from Gate Oxide Short", A. Yassine, K. Wieczorek, K.
Olasupo & V. Heinig, AMD
Wednesday afternoon is free for discussion, hiking & other recreation;
or for viewing videos shown in parallel:
(1) Oxide Wearout/Breakdown/Reliability (Angora Room); (2) MEMS
Performance and Reliability (Cathedral Room)
Session #6: Contributors to Failure (CTF), Chairs: Homi Nariman, AMD, &
Prasad Chaparala, National Semiconductor
- CTF-5
- "Threshold Voltage Drift in PMOSFET´s due to NBTI &
HCI", P. Chaparala, National Semiconductor, P. Lim, Stanford University,
& J. Shibley, National Semiconductor
- CTF-6
- "Negative Bias Temperature Instability (NBTI) in Deep Sub-micron
p+-gate pMOSFETs", C.H. Liu, Y.F. Chen, S.K. Fan, M.T.
Lee, M.H. Lin, C.H. Chou, W.C. Chang, S.C. Huang, Y.J. Chang, & K.Y. Fu,
United Microelectronics Corp.
- CTF-7
- "Improving the Accuracy of "Shift & Ratio" Channel
Length Extraction Method In Deep Submicron Technology", Q. Ye, Infineon,
Y. Li, W.R. Tonti, W. Berry, C. Parks, & R. Mohler, IBM Microelectronics
- CTF-8
- "Reliability of Via & Its Diagnosis by E-Beam Probing", W.
Xia, M. Villafana, J. Tappan, T. Watson, & M. Campbell, Qualcomm Inc.
Session #7: Contributors to Failure (CTF), Chairs: John Conley, NASA JPL
& Abdullah Yassine, AMD
- CTF-9
- "Modeling Trap Generation Process In Thin Oxides", G. Bersuker,
Y. Jeon, G. Gale, J. Guan, & H. Huff, SEMATECH
- CTF-10
- "Identification of Atomic Scale Defects Involved in Oxide Leakage
Currents", P.M. Lenahan, J.J. Mele, Penn State Univ., S.T. Liu, Honeywell,
R.K. Lowry & D. Woodbury, Intersil
- CTF-11
- "Stress-Induced Leakage Current Comparison of Giga-bit Scale DRAM
Capacitors with OCS (One-Cylinder-Storage) Node", D. Park, H. Ban, S.
Jung, H. Yang, & W. Lee, Samsung Electronics