Keynote

Defect Generation and Reliability of Ultra-thin SiO₂ at Low Voltage—D.J. DiMaria and J.H. Stathis, IBM, Yorktown Heights, NY

The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently a concern has been raised that the reliability of ulrathin SiO₂ layers may limit the continued scaling of gate oxides less than about 2nm. In this talk we will review the physics of oxide breakdown. Electrons tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only < 1% of the these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases exponentially with supply voltage, below a threshold voltage of about 5V for hot electron induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a diminishing margin for reliability as device dimensions are scaled.

Tutorials
Chair: Douglas R. Menke, Motorola

Managing Technology Qualification in a Foundry/Fabless Partnership—Raif Hijab, Cirrus Logic

Tutorial Session #1A Monday, 1:30–3:30 p.m.(Angora Room)

This tutorial addresses the qualification requirements of a new foundry technology in the emerging foundry/fabless semiconductor manufacturer model. It describes the key steps involved in assuring that the foundry technolgy meets the minimum performance and reliability needs of the semiconductor manufacturer. This topic is of interest beyond the pure foundry/fabless house community, since many IDMs are contracting out a major portion of their semiconductor wafer manufacture, while many are offering foundry services to absorb any idle capacity they might have. This has highlighted the need for more widely accepted qualification criteria, and a uniform language and format of exchanging qualification data between foundry and customer.

The tutorial will cover discussion of the methodology outlined in the JEDEC/FSA draft procedure "Standard Foundry Process Qualification Guidlines", which has been submitted for JEDEC letter ballot. This includes the minimum set of measurements required to qualify a semiconductor wafer process, applicable standards, responsibilities of foundry and fabless house, and reporting requirements. The tutorial will also address the question of ongoing reliability monitoring, and how it leverages both PCM electrical data and wafer level reliability monitor data.

Integrated Circuit Fabrication Technology and Yield Control—Ernest Levine, Tom Houghton, and Parth Dave, IBM

Tutorial Session, 1B & 2B, Monday, 1:30–5:45 p.m. (Old Lodge)

This tutorial details in a step-by-step fashion (from buying the wafer up to the final interconnect structure made by Cu damascene techniques) how a logic chip is built and what are the associated yield control/metrology steps encountered during fabrication. The basic steps, which are applicable to any state-of-the-art chip facility, will be described in such detail that the attendee will understand the reason for each step, the logic of the sequence used, as well as the systematic and random defects that may be encountered. Additionally, a discussion of an active yield control strategy will be described, including in-line inspection techniques and points, use of CD, overlay, and AFM — both now and in the near in future. Cross sections, top-down defect appearances, etc. at each key step will be used to illustrate the fabrication process and the defects found. Methodologies used to track down root causes of various failure mechanisms will be discused and illustrated.

Ultra-Thin Gate Oxide Reliability for ULSI Applications—Ernest Y. Wu, IBM Co. Microelectronics Division

Tutorial Session #2A, Monday, 3:45–5:45 p.m. (Angora Room)

The aggressive scaling of gate oxide thickness for high performance and density in microelectronics industry has reached an unprecedented pace. The extraordinary demand of oxide thickness reduction raises serious concerns for oxide reliability. In this tutorial, the current status and future perspectives of ultra-thin gate oxide reliability will be reviewed. Various reliability evaluation measurements and methodologies are critically examined. Breakdown statistics and percolation model are discussed in light of recent finding of thickness-dependent Weibull shape factors. The measurement techniques of Weibull characteristic parameters are discussed. The issues of microscopic and macroscopic oxide thickness uniformity are considered. Their impact on Weibull breakdown characteristics and oxide reliability is addressed in detail. Various projection schemes in terms of voltage vs. field and time-to-breakdown vs. charge-to-breakdown are discussed. Relative importance of breakdown characteristic time and Weibull shape factor is highlighted using a two-dimensional reliability analysis. The current knowledge of voltage and temperature dependence of time (charge)-to-breakdown is reviewed in the framework of several published models. Finally, different breakdown modes (soft vs. hard breakdown) are reviewed with the emphasis on physical origin, post-breakdown conduction properties, and current runaway dynamics. The implications of different breakdown modes for transistor characteristics and circuit operations are discussed. It is concluded that all above aspects should be carefully and thoroughly considered in oxide reliability evaluation and projection.

Discussion Groups

Chair: William J. Vigrass, Texas Instruments

The evening discussion group program is regarded as a favorite highlight of the workshop experience. Attendees will have a choice of 4 topics on both Tuesday and Wednesday evening. Topics 4 and 5 will be offered only once on Tuesday and Wednesday, respectively. You are encouraged to bring along data and/or ideas on transparancies for discussion in the discussion group.

1. WLR Monitoring:
Andreas Martin, Infineon Technologies &
Eric Snyder, Sandia Technologies

Wafer Level reliability, or WLR, refers to a category of stresses which are performed by directly applying temperature, voltage, and/or current stress on specially designed test structures, thus quickly providing data on a wide range of reliability issues. Because of their flexible design and use, WLR tests have become pervasive in the Microelectronics Industry, for applications ranging from technology/process development, to the monitoring of manufacturing lines. By and large, the success of WLR has resided in its ability to provide useful data at elevated stress conditions in a very small amount of time (sec to min), compared to package-level testing. In a fast paced, high volume development or production environment, stepping from traditional WLR to fast WLR is easily done. But what exactly is fast WLR, and how can it be useful to you and your boss?

We hope that by participating in this discussion group, you will come away with answers to these, and other questions, such as:

• Advantages/disadvantages of fast WLR.

• Is traditional WLR fast enough?

• How widely is fast WLR used and should you switch?

• Use which physical models for the interpretation of fast WLR data?

• Success stories, etc.

2. Ultra-Thin Oxides:
Daniel DiMaria, IBM and
John Suehle, National Institute of Standards & Technology

Recent reports indicate that SiO₂ may be able to be scaled down to 1.6 nm. Characterizing gate oxides in this thickness regime presents new challenges in terms of reliability testing, analysis, and projection. The aggressive scaling of oxide thickness has raised several important questions:

• Is intrinsic reliability being compromised?

• Are the physics of failure different than thicker gate oxides?

• Do we know what we are doing when characterizing ultra-thin films?

• When will high-k films be required?

Some of the issues to be addressed include hard and soft breakdown, acceleration parameters for TDDB, the effect of soft breakdown on circuit performance, physical models for oxide breakdown, and testing techniques. Participants are invited to present any new results or ideas to help clarify or further confuse these issues.

3. Electromigration:
Harry A. Schafft, NIST and
Tim Sullivan, IBM Microelectronics

Focal points for discussion will include the following:

• Observations and issues in Al-based metallization, such as comparison of and/or standardization of structures for qualification purposes, and effects of test structure design on test data.

• EM in Cu metallizations; differences from Al, (e.g., linewidth dependence, deposition method, etc.); failure criteria, possible pitfalls of high-temperature testing.

• Wafer level and package level EM for both Cu and Al; effects of different structures on failure distributions, self-heating, and test algorithm.

• Effects of low-K dielectrics on EM and EM testing.

The intent of the discussion group will be to explore areas of interest to the participants in a casual environment. The moderators will have material to stimulate discussion, but no set agenda will be followed.

4. Burn In:
Raif Hijab, Cirrus Logic Inc. and
Rolf P. Vollertsen, Infineon Technologies

Burn-In is an integral part of IC productions. It serves to screen weak parts and improve the failure rate during early life. Besides this benefit it is expensive and it might degrade intrinsic properties by the high stress conditions or introduce additional fails due to ESD or handling problems. Considerations on how to reduce Burn-In cost and increase screen efficiency lead to concepts like wafer level Burn-In or IDDQ measurements. However, the success of alternative measures depends on the failure mechanism.

The goal of the discussion group is to sample the experience with Burn-In among the participants, evaluate recent developments and discuss possible strategy changes to address future needs. Discussion topics of interest are:

• How effective is Burn-In in general and for certain failure mechanisms?

• What are the risks of Burn-In and how to limit those?

• Why is the usefulness of Burn-In product dependent?

• How can Burn-In be optimized?

• Do we need Burn-In at all and why?

• How to replace or eliminate Burn-In?

• What are the alternatives and do they work reliably?

5. NBTI:
Emmanuel Vincent, STMicroelectronics &
Brian Langley, Agilent Technologies

Deep-submicron technologies encounter a novel failure mechanism associated to MOS device threshold voltage shift after gate stress under elevated temperature. This phenomenon, so-called (Negative) Bias Temperature Instabilities (NBTI) impacts more likely on P-channel MOS devices and may affect especially the analog block reliability.

Topics to be debated during this discussion group include:

• Underlying physics

• Test methodologies and procedures

• Test structures

• Effects on PMOS vs. NMOS...

Special Interest Groups

Chair: William Vigrass,Texas Instruments

The Special Interest Groups (SIGs) program at the Workshop has been very successful in fostering collaborative work on important reliability issues and we look forward to continuing growth and renewal in our SIGs. The formation of SIGs is encouraged as a natural extension of the Discussion Group sessions. Anyone interested in more information on SIGs see http://www.iirw.org/sig/.

Refereed & Open Poster Sessions
(Monday & Wednesday Evening)

Chair: Rolf Vollertsen, Infineon Technologies

We have 15 refereed posters! In addition, all attendees have the opportunity to present a poster to communicate and discuss their ideas and newest results on technical projects or issues. Please indicate your intention to bring a poster by reserving a poster display board (32" × 40" or 81 cm × 100 cm) in the space provided on the registration form. Your work should be in Landscape format on 8½ × 11" or A4 paper with a maximum of twelve pages. In addition, you are invited to submit a two-page abstract of your poster presentation for inclusion in the Workshop Final Report. See www.iirw.org/00/poster/2000 for details and deadlines. This is a great opportunity for you to share your work with your peers. If you are presenting a refereed or invited poster a display board will be reserved for you.