In spite of the hard economic times and the 9/11 terrorist attacks, IRW 2001 was held (10/15/18) at the Stanford Sierra Camp located on Fallen Leaf Lake (just off the southern tip of Lake Tahoe). Forty-four researchers, engineers, and educators attended this years workshop, all with the same mindset: It's time to go back to work and advance microelectronic reliability.

General Chair Dr. Andreas Martin (Infineon Technologies) and Technical Program Chair Dr. Linda Head (Rowan University), together with the excellent IRW volunteer management team, Put together a strong program of a keynote address, 6 tutorials, 13 platform presentations, and discussion group and special-interest group meetings that rivaled past IRW. The keynote was on the advancement and integration of praseodymium oxide, a high K dielectric, for use in next generation advanced silicon based technologies. Dr. Andreas Martin presented the keynote for Dr Hans-Joachim Mussig of IHP (Germany), who was not able to fly to the States. This atypical situation occurred for a few papers where the papers were delivered by the mentor of the papers. The IRW community is a close-knit group, with mentors and authors working together to perfect the platform address and paper, published in the IRW Final Report (proceedings). As usual, the presentations were taped and given to the authors to use in preparing the questions and answers for inclusion in their published paper. The Final Report (proceedings), in hard copy and in CD-ROM, can be ordered from http://www.irps.org or by e-mail: becky@sar101.com.

Of the many highlights within the technical sessions of the conference this year, was the impressive strength of the tutorial program. Six speakers shared their extensive knowledge and perspectives, while answering all questions and establishing an unusual level of personal interaction and rapport. Dr. Eric Vogel (NIST) reviewed the state of dielectric reliability and of the present reliability physics models. Dr Patrick Lenahan (Penn. State University) provided a comprehensive understanding of the physical nature of dielectric reliability, E' centers, and the tools used to detect these defect centers. Dr. Gennadi Bersuker (Sematech) extended Vogel's and Lenahan's work to link the present physical understanding with a new electrical model, building on the weakness and strengths of the present state–of–the–art models. Dr. James McVittie (Stanford University) and Dr. Nguyen D. Bui (Lattice Semiconductor Corp.) gave complementary perspectives on the nature of process–induced charging and microelectronic damage. Dr. Zhihong Liu (Celestry Design Technologies, Inc.) presented compact reliability circuit simulation techniques and the benefits of using them to optimize full–chip design and reliability considerations.

The platform presentations included state–of–the–art papers covering a wide range of topics, briefly summarized here.

Given today's low internal voltages (1-1.5V), there still exists a need for high voltage power management (20-30V), and the integration of these devices in a silicon package. Power management and hot carrier design and protection of such integration becomes a very complex problem as the differences in the power supply requirements for these high–voltage / low–voltage devices widen. New findings on the geometric design, simulation, and verification testing of high voltage N-LDMOS transistors was presented by Dr. Douglas Brisbin (National Semiconductor Corp.)

The required scaling of the PMOS transistor, as shown in the SIA roadmap, has led technology from buried channel, single work–function CMOS, to dual work–function, fully–scaled CMOS, having both surface channel NMOS and PMOS devices. The PMOS gate electrode has migrated from N+ to P+ doping in this transition from buried to surface channel operation. Over the years, researchers have solved the reliability problems associated with boron penetration through the gate of the PMOS surface channel device (this is not an issue for N+ gated buried channel PMOS), but a new mechanism affecting surface channel PMOS transistors called "negative–bias temperature instability" remains to be solved. This new reliability mechanism, normally affecting surface channel PMOS transistors and called "negative bias temperature instability", was first presented at IRW 2000 by Dr. Prasad Chaparala (National Semiconductor Corp.), and was investigated further this year by Dr. Hisoa Katto (Science University of Tokyo). Dr. Katto methodically investigated both surface channel NMOS and PMOS transistors. He finds an additional positive gate bias instability for the PMOS transistor, and a negative bias instability for NMOS devices. The negative bias PMOS instability remains the most damaging mechanism in these new high performance CMOS technologies.

As lithography scales, the drive towards lower power supplies and reduced power carries with it the need for ever thinner gate oxide systems. The traditional SiO₂ system, used in the majority of all gate dielectrics, begins to lose it's appeal as reliability problems begin to dominate gate oxides that are thinner than about 20 angstroms. The drive towards replacing gate oxides with "high-K" dielectrics (which permits thicker films to be used) becomes appealing from both a manufacturing control and defect standpoint, as well as from reliability problems associated with such very thin SiO₂ films. Dr. John F. Conley Jr. (Sharp Laboratories of America) presented a first look at high–K Hafnium Oxide (HfO₂) films deposited by atomic layer chemical vapor deposition. The resultant dielectric constant of this material is between 8 and 8.6 versus 3.9 for the SiO₂ system. The dielectric constant of Pr O₂, described in the keynote, is approximately 30.

The introduction of copper and copper low–K systems has led to many developments in test methodology and the integration of copper into today's high speed CMOS and BiCMOS circuits. Copper affords a large reduction in metal resistivity over the standard Al systems presently used. This implies copper can take advantage of the improved lithography as smaller lines can be used for equivalent Al resistances. Unlike the high–K MOS dielectric discussion above, the back–end–of–line metal system link to circuit performance is driven by the RC delay of the line. While the resistance component is dominated by the copper line itself, the capacitive component is shared by both it's intra– and inter–level neighbors, and the move to higher density drives tight line pitch and thus is the enabling force in the development of a low–K, back–end–of–line interconnect system. This nets a realizable improvement in the RC delay of the metal system. One of the problems associated with either a low–K or a high–K back–end–of–line copper system is the reliability of inter–level diffusion among neighboring copper lines. Dr. Glenn B. Alers (Novellus) presented an overview of this reliability

mechanism and demonstrated a fast wafer level reliability testing and analysis technique used to monitor this problem.

In–line process charging has long been a reliability mechanism that is very difficult to control and isolate as it generally is related to a tool problem manifesting itself long before a product wafer reaches test. This is the subject of two tutorials described above and of a paper by Dr. David Smeets (Infineon Technologies), where a guideline and test procedure was presented on using antenna structures for fast wafer–level reliability testing and monitoring of process–induced damage.

One technology enabled by copper metallurgy is today's advanced BiCMOS silicon germanium heterojunction or HBT devices. Operating at frequencies beyond 200 GHz, these transistors can be characterized as typically "on" and conducting as contrasted to it's neighboring CMOS which typically has a conducting duty factor of approximately I% and is normally "off'. The electromigration reliability of these devices and associated interconnects must be well known in order to place such products in the field. Kevin Brelsford (IBM MicroElectronics) discussed the electromigration limitations of HBT transistors, where device self heating plays a critical role in it's intrinsic limit. This was followed by a discussion of improved design practices providing reliability margin for these devices.

CMOS and BiCMOS designs are pushing the envelope of analog and mixed–signal applications, where frequently the analog core is designed in CMOS. In addition to the time–zero control of MOSFETs and parasitics used in analog operation, the concern of analog drift under circuit aging must be incorporated into the design of a reliable product. Yuan Chen (Agere Systems) investigated the analog mismatch associated with hot carrier transistor aging and negative–bias temperature instabilities and the design practices that can mitigate some of these instabilities.

The evening discussion group meetings covered the topics of advanced dielectrics, copper metallurgy, device reliability, and product burn–in. The product burn–in session reviewed various ways foundries qualify a technology reliability and how this enables a product qualification and feedback when problems arise. A discussion was pursued on the product reliability evaluations of a digital part versus an analog part. Typically, the test vectors in a digital part can guarantee 100% burn–in at accelerated conditions, while the same is not true for the analog part. Further complicating analog burn–in is the unknown circuit operation at accelerated conditions. The discussion group on copper led to the formation of a special interest group that will function after the workshop. The purpose of group is to develop guidelines for the design and use of test structures and the analysis of their fail–time data to characterize Cu Lo–K interconnects for electromigration, inter–line reliability, and stress migration.