as of August 18th
pending authors' confirmation
Session Hot Carrier Degradation, SHD: 1. Bias and Temperature Dependent Hot-Carrier Characteristics of Sub-100nm Partially Depleted SOI MOSFET's 2. Hot-Carrier Degradation of n-channel MOS LDD Devices under Dynamic Stress Conditions 3. Hot Carrier Luminescence for Backside 0.15um CMOS Device Analysis 4. 1-D and 2-D Hot Carrier Layout Optimization of N-LDMOS Transistor Arrays Session High-K Dielectrics, HKD: 1. Polarity Dependent Reliability of Advanced MOSFET Using MOCVD Nitrided Hf-silicate High-k Gate Dielectric 2. Thermal and Dielectric Breakdown for metal insulator metal capacitors w/ tantalum pentoxide dielectric 3. Reliability Concerns for HfO2/Si Devices: Interface and Dielectric Traps 4. Electrical Propeties and Reliability of HfO2 Deposited via ALD Session Thin Oxide Reliability, TOR: 1. Evidence that the progressiveness is defect generation probability driven 2. Defect Generation in Ultra-thin Oxide Over Large Fluence Ranges 3. Comparison of Low Leakage and High Speed deep Submicron PMOSFET's submitted to hole injection 4. Conducting Atomic Force Microscopy Studies for Reliability Evaluation of Ultrathin SiO2 Films 5. Parametric Reliability Test: Wafer Surface Contamination Study Session NBTI Phenomenon, NBT: 1. Negative bias temperature instability of deep sub-micron p-MOSFETs under pulsed bias stress 2. The Impact of NBTI and HCI on Deep Sub-micron PMOSFETs' Lifetime 3. Model for NBTI in p-MOSFETs with ultra thin nitrided gate oxides 4. Interface traps and oxide charges during NBTI stress in p-MOSFET Session Cu interconnect, CUI 1. Adhesion and Electromigration in Cu Metallization 2. Intra_metal Leakage Reliability Characterization for the Line/Via combined Structures in Copper/Low-k Interconnect Process 3. Extrapolation of Highly Accelerated Electromigration Tests on Copper to Operation Condition 4. Temperature Determination Methods on Copper Material for Highly Accelerated Electromigration Tests (e.g. SWEAT) 5. A Practical Methodology for Multi-modality Electromigration Lifetime Prediction 6. Electromigration simulation of Cu-Low k multi-level interconnect segment 7. Effect of reduced current density stress on the results of isothermal electromigration test for Cu damascene lines Session Product Reliability, PRR: 1. Fast and Reliable WLR Monitoring Methodology for Assessing Thick Dielectrics Test Structures Integrated in the Kerf of Product Wafers 2. Gate reliability correlation between test structure and DRAM product chips 3. Direct correlation of electrical reliability data to SEM analysis for deep trench dielectric weakness 4. Fast wafer level monitoring of stress induced leakage current in deep sub-micron embedded non-volatile memory processes 5. Wafer-level Assessment of SiGe NPN HBTs after High Temperature Electrical Operation 6. Time-dependent Dielectric Breakdown Evaluation of Deep Trench Capacitor With Sidewall Hemispherical-grained Silicon For Gigabit DRAM Technology