PROGRAM ANNOUNCEMENT!

'03 Workshop Features:

Keynote:

 "The Complete
Metrology Roadmap,"
Alain C. Diebold,
International SEMATECH, USA

Tutorials

    Non-Contact Methods for In-Line Reliability Determination
    Fast Wafer Level Reliability Monitoring of Product Wafers
    MRAM and Reliability
    Reliability Physics and Chemistry of Thin and High-k Gate

Group Discussions
Special Interest Groups
Responsibility of Attendee
JEDEC 14.2
Questions ?

19 Technical Presentations on:

  • Customer Product Reliability Requirements
  • Ultra-Thin Oxides & High-K Dielectrics
  • Circuit Level Reliability
  • Hot Carriers and Memory Reliability

Refereed/Open Poster Sessions

16 Accepted posters

Three Training Videos:

  • Oxide Wearout/Breakdown/Reliability
  • MEMS Performance & Reliability
  • Accelerated Stress Testing

You are cordially invited to participate in the 2003 Integrated Reliability Workshop. It provides a unique environment for envisioning, discussing, and developing reliability technology for present and future semiconductor applications. Here you will closely interact with your peers at moderated discussion groups, open poster sessions, technical presentations, and special interest groups. All Workshop activities take place in a relaxed and rustic setting that promotes an atmosphere of interactive learning.

Major Technical Themes

As industry retools and regroups for the coming technology sector expansion, it is crucial that the reliability of new materials, devices, and products be kept at the forefront of development and design of new products. The Integrated Reliability Workshop is focused this year on exactly this mission.

On Monday, we are leading our program this year with tutorials on three diverse but important topics in materials and product reliability, "Theory and Application of Non-Contact Methods for In-Line Reliability Determination," by John D'Amico, Semiconductor Diagnostics, Inc., "Fast Wafer Level Reliability Monitoring of Product Wafers" by Andreas Martin, Infineon Technologies, and "MRAM and Reliability" by Brian Hughes, Infineon Technologies.

An additional tutorial session on Tuesday includes a late-breaking news presentation "Reliability Physics and Chemistry of Thin and High-k Gate Oxides" by Pat Lenahan, Penn State, which addresses new materials reliability issues in detail.

Our keynote picks up on another important theme, metrology and physical characterization for new technologies. It is "The Complete Metrology Roadmap" by Alain C. Diebold, International SEMATECH Senior Fellow.

You will have ample time for one-on-one exchange, organized discussion groups, our popular and productive SIGs (Special Interest Groups) and poster sessions where all our attendees are encouraged to display a poster with their most recent work, ideas, and results. As a very special feature, you are offered the opportunity to view three recent IEEE sponsored videos: "Oxide Wearout/Breakdown/Reliability," "MEMS Performance & Reliability," and "Accelerated Stress Testing." To purchase these videos for your organization is costly but IRW attendees can view them free of charge at the Workshop.

Inform your colleagues about the workshop and spread the word, so nobody misses the chance to participate and benefit. Inform your management. Your organization will not want to miss this investment in education on how to deal with today's reliability issues and prepare for the ones of tomorrow.

Keynote

The Complete Metrology Roadmap

Alain C. Diebold, International SEMATECH, USA

The Metrology Roadmap is now a well established part of the International Technology Roadmap for Semiconductors. The Metrology Roadmap describes the measurement requirements and potential solutions for lithography, front end processes, and interconnect processes. The Metrology Roadmap hopes to link together measurement needs and process requirements. One well known example of this connection is to calculate the precision required for measuring the thickness of a gate dielectric when the allowed process range is 4% to 3s. The precision requirements for many measurements are notoriously difficult to meet. Based on the precision requirements for future technology generations, critical dimension control will be difficult to maintain using known measurement methods (CD-SEM, scatterometry, etc.). An extended discussion of the Metrology Roadmap including Materials Characterization will be provided

Tutorials

Chair: Amr Haggag, Motorola
Tutorial #1 Monday, 1:30_3:30 p.m.(Angora Room)

Theory and Application of Non-Contact Methods for In-Line Reliability Determination

John D'Amico, Semiconductor Diagnostics, Inc.

Over the last decade, the IC industry has labored vigorously to maintain Moore's law. Success, in large part, has been due to realizing critical milestones – such as transitioning to larger diameter wafers, integrating Cu and Low K interconnects, and pushing the physical boundaries of the gate oxide – not to mention overcoming the countless other processing and integration challenges encountered. During the same time, the cost invested per wafer, as measured by the number and complexity of the processes, has grown significantly. Naturally, to protect the investment and maximize efficiency, there is gravitation toward in-line, real-time reliability monitoring to identify and diagnose issues before they kill yield.

In this regard, in-line monitoring of the front-end diffusion area has become increasingly more common and mature. Numerous non-contact measurements are now available that provide fast feedback of parameters ranging from silicon lifetime to gate oxide integrity. This tutorial provides an in-depth examination of the theory and application of in-line characterization methods developed from two fundamental non-contact measurement techniques, Surface Photovoltage (SPV) and Contact Potential Difference (CPD), and their response to stress created by dielectric charging with a corona discharge in air. Specific topics include monitoring of heavy metal contamination, mobile ion contamination, leakage current, and interface and dielectric traps, with an emphasis placed on reliability issues for ultra-thin gate dielectrics.

Tutorial #2, Monday, 4:00_6:00 p.m. (Angora Room)

Fast Wafer Level Reliability Monitoring of Product Wafers

Andreas Martin, Infineon Technologies

This tutorial gives an overview of the current state of the art of fast Wafer Level Reliability (WLR) monitoring. Fast WLR is an essential tool for a continuous quality control in a production environment to verify the process reliability beyond process qualification on product wafer material. This in-line testing method, taking a few seconds per test item, guarantees shortest feedback cycles into production to detect process reliability deviations. Of course, it can be also employed before process qualification, during process development.

This tutorial describes the main aspects and highlights problem areas of: test structure design for scribe lines, stress and measurement sequence creation, tester hardware, analysis/reporting and sampling. It discusses the controversy between qualitative and predictive fast WLR, how to use fast WLR even without a physical model for the degradation mechanism. The typical areas of dielectric reliability (MOS gate dielectrics, back end of line capactiors, intermetal dielectrics), device degradation (Hot Carrier, negative bias temperature instability, mobile ions), metallisation reliability (electromigration, contact and via integrity) and effects of plasma induced damage are covered. Relevant publications of the field are stated for further studies.

Tutorial #3, Monday, 7:30_8:30 p.m. (Angora Room)

MRAM and Reliability

Brian Hughes, Infineon Technologies

This tutorial will provide an overview of the design, operation, and materials of Magnetoresistive Random Access Memory (MRAM) with emphasis from a reliability engineering perspective. The speaker will provide background information on MRAM architectures and discuss novel reliability problems inherent to MRAM. Reliability issues and concerns will be discussed and illustrated with examples wherever possible. The intention of the tutorial is to give attendees a basic and broad introduction to the reliability challenges raised by this novel memory form.

Tutorial #4, Tues., 1:00_3:00 p.m. (Cathedral Room)

Reliability Physics and Chemistry of Thin and High-k Gate Oxides

Pat Lenahan, Pennsylvania State University

The International Technology Roadmap for Semiconductors indicates that fundamental limits to downscaling will be reached by 2005. At the present time, there is therefore great technological interest in very thin SiO2-based dielectrics as well as in "new" significantly higher dielectric constant (high-k) materials such as HfO2, ZrO2, and hafnium and zirconium silicates. These new oxides have considerable promise but many recent studies demonstrate that devices based upon these and other high-k oxides exhibit potentially serious reliability problems which are as yet poorly understood. This tutorial will review recent work of a number of groups investigating dielectric charge trapping, interface traps, low channel mobilities, and other problems in new high-k oxide/silicon systems. This review will be integrated with a discussion of somewhat better understood problems in very thin SiO2-based dielectric/silicon systems. This presentation will also include a comparison of atomic scale defects involved in hafnium oxide – hafnium silicate, zirconium oxide – zirconium silicate, and silicon dioxide based systems.

Refereed & Open Poster Sessions

Chair: Bill Tonti, IBM Engineering & Technology Services

(Monday & Tuesday Evening)

There are 15 accepted posters (listed below). They cover: hot carriers, negative bias temperature instability, interconnect reliability, and fast gate oxide wafer reliability methodologies. Each refereed poster author will deliver an oral presentation on their results during the poster sessions.

In addition to the already accepted posters all IRW attendees are invited to bring a walk-in poster to communicate and discuss their reliability work in progress, or late breaking results. This is a great opportunity to obtain feedback and perhaps collaborate with your peers. Please indicate on the registration form your intention to bring a walk in poster by reserving a poster display board. In addition, you are invited to submit a paper of your poster presentation for inclusion in the Workshop Final Report.

Additional information can be found at: http://www.irps.org/irw/poster/.

REFEREED POSTERS

P1 Reliability of dielectric barriers in copper damascene applications—A. Lee, A. Lakshmanan, N. Rajagopalan, Z. Cui, M. Le, L.Q. Xia, B.H. Kim, and H. M'Saad, Applied Materials

P2 Latch-up failure path between power pins in the mixed-voltage process—C.-N. Wu, H.-M. Chou, and M. Chang, TSMC

P3 Effect of reverse measurement on the HC instability evaluation of MOSFETs—H. Katto, M. Miyauchi, and Y. Higuchi, Tokyo University of Science

P4 NBTI mechanism explored on the back gate bias for pMOSFETs—M.-G. Chen, J.-S. Li, C. Jiang, C.H. Liu, K.-C. Su, and Y.-J. Chang, United Microelectronics Corp.

P5 A design technique to reduce hot carrier effect—E. Xiao, University of Texas at Arlington

P6 Determination of the maximum voltage for a product screening stress without jeopardizing the product lifetime, based on wafer level TDDB and HC measurements—H.-H. Kuge, Philips Semiconductor

P7 Calculations of electronic and elastic properties of Cu-interconnects—Y.N. Shunin, K. Budilov, Information System Institute &Transport and Telecommunication Institute, Y. Zhukovskii, University of Latvia, G. Borstel and O. Sychev, Univ. Osnabrück

P8 Effect of joule heating on the determination of electromigration— X. Federspiel, Philips Semiconductors, V. Girault, and D. Ney, STMicroelectronics

P9 Correlation of ramped current to constant voltage gate oxide reliability testing on leading edge DRAM technology—G. Aichmayr and A. Beyer, Infineon Technologies

P10 Effect of nitrogen incorporation on PMOS negative bias temperature instability in ultra-thin oxy-nitrides—L. Duong, V. Gopinath, S. Prasad, J. Lin, E. Li, and V. Hornback, LSI Logic Corporation

P11 Effect of new inter-layer-dielectric on plasma charging damage in 0.13 µm dual gate oxide— W.H. Lu, L.H. Ko, K.L.Y. Andrew, and K.F. Lo, Chartered Semiconductor Mfg. Ltd.

P12 Impact of junction temperature on microelectronic device reliability and considerations for space applications—M. White, M. Cooper, and Y. Chen, JPL

P13 Massively parallel GOI test—T.K. Ng, K.F. Lo, B.B. Jie and Y. Andrew, Chartered Semiconductor Mfg. Ltd.

P14 Reliability results on a 0.25 micron aluminum backend with a TiN Liner—L. Westergard, M. Nelson, B. Williams, and J. Prasad, AMI Semiconductor

P15 HCI lifetime enhancement by PLDD implant energy optimization of Pch MOSFET in 0.13 µm CMOS technology—L. Hyeokjae, E. Quek, Y. Andrew and M. Fakhrulkarim, Chartered Semiconductor Mfg. Ltd.

P16 Similarity of Pre-Breakdown Leakage Current Fluctuations for p- and nMOSFETs—J.C. Reiner, EMPA

Discussion Groups

Chair: Sylvie Bruyere, STMicroelectronics

The evening discussion group program is regarded as a favorite highlight of the workshop experience. Attendees will have a choice of at least two areas on Tuesday and Wednesday evenings. The topics to be discussed will be at the discretion of those participating in the group. Each group is assigned a pair of leaders who have extensive experience with the area and will help to guide the discussion. Everyone is encouraged to bring along data and/or ideas to share on topics that are of particular interest. As we get closer to the date of the workshop, we will be surveying registered attendees so that we may prepare relevant discussion outlines to be distributed at the camp.

Special Interest Groups

Chair: Sylvie Bruyere, STMicroelectronics

The Special Interest Groups (SIGs) program at the Workshop has been very successful in fostering collaborative work on important reliability issues and we look forward to continuing growth and renewal in our SIGs. The formation of SIGs is encouraged as a natural extension of the Discussion Group sessions. Anyone interested in more information on SIGs see http://www.irps.org/irw/sig/.

Responsibilities of Attendees

You are expected to come prepared to participate actively in the discussions and meetings by sharing your experiences, concerns, questions, views, technical information, and test data, as appropriate. Your active involvement in the formal, as well as in the informal meetings and activities, is the key ingredient for maximizing the value of the workshop for you and your fellow attendees.

JEDEC 14.2 Meeting. The JEDEC 14.2, Wafer Level Reliability Standards Committee, meeting will be held immediately after the Workshop at the Stanford Sierra Camp on Thursday afternoon and Friday morning. Members, alternates, and guests are welcome. The cost for the accommodations is $200, which includes Thursday night dinner and lodging and Friday breakfast and lunch. All attendees must leave the camp after lunch on Friday. If you have any questions or if you want to become a member of JC-14.2, please call the JEDEC office at (703) 907-7558 or www.jedec.org, or call Mike Dion, JC-14.2 Chair at (321) 724-7067.

Questions? If you have any questions, please contact either: Technical Program Chair, Alvin Strong, by phone, (802) 769-1326, fax..4287, or email: astrong@us.ibm.com; Technical Program Vice Chair, Rolf Vollertsen by email: rolf.vollertsen@infineon.com; or General Chair, Gennadi Bersuker, by phone (512) 356-7045, email: gennadi.bersuker@sematech.org.

REGISTER NOW!

Complete and send in the enclosed registration form. Please register early. Space at the Camp limits IRW to approximately 120 attendees.

We expect an exciting workshop again this year. We look forward to your active participation in the many Workshop activities and your valuable contribution to the technical discussions.

We look forward to seeing you at the Workshop!

Sincerely,
Alvin Strong
Technical Program Chair