The poster session of the IRW 2003 will showcase two kinds of posters:
If you are presenting a refereed or invited poster a display board will be reserved for you. For both, the refereed and open posters the display board area is 32" × 40" or 81 cm × 100 cm. Your work should be in Landscape format on 8½ × 11" or A4 paper with a maximum of twelve pages. Details and deadlines for preparation of the abstract for inclusion in the IRW Final Report can be found in "Instructions for posters to be included in Final Report" below.
Last minute posters - bring your poster directly to the IRW.
We encourage presentation of your latest ideas and newest results on technical
projects or issues by accepting your poster upon your arrival at the workshop
(see the Technical Poster Chair). If possible please indicate your intention to
bring a poster by reserving a poster display board in the space provided on the
registration form or/and sending an e-mail to the Technical Poster Chair by
10/15/03. The poster size is the same as for the refereed and open posters. No
paper can be included in the final report in this case.
Instructions for posters to be included in Final Report pdf version or word doc
Poster Presentation in Final Report Example (pdf)
IEEE Copyright Form
P1 Reliability of dielectric barriers in copper damascene applications—A. Lee, A. Lakshmanan, N. Rajagopalan, Z. Cui, M. Le, L.Q. Xia, B.H. Kim, and H. M'Saad, Applied Materials
P2 Latch-up failure path between power pins in the mixed-voltage process—C.-N. Wu, H.-M. Chou, and M. Chang, TSMC
P3 Effect of reverse measurement on the HC instability evaluation of MOSFETs—H. Katto, M. Miyauchi, and Y. Higuchi, Tokyo University of Science
P4 NBTI mechanism explored on the back gate bias for pMOSFETs—M.-G. Chen, J.-S. Li, C. Jiang, C.H. Liu, K.-C. Su, and Y.-J. Chang, United Microelectronics Corp.
P5 A design technique to reduce hot carrier effect—E. Xiao, University of Texas at Arlington
P6 Determination of the maximum voltage for a product screening stress without jeopardizing the product lifetime, based on wafer level TDDB and HC measurements—H.-H. Kuge, Philips Semiconductor
P7 Calculations of electronic and elastic properties of Cu-interconnects—Y.N. Shunin, K. Budilov, Information System Institute &Transport and Telecommunication Institute, Y. Zhukovskii, University of Latvia, G. Borstel and O. Sychev, Univ. Osnabrück
P8 Effect of joule heating on the determination of electromigration— X. Federspiel, Philips Semiconductors, V. Girault, and D. Ney, STMicroelectronics
P9 Correlation of ramped current to constant voltage gate oxide reliability testing on leading edge DRAM technology—G. Aichmayr and A. Beyer, Infineon Technologies
P10 Effect of nitrogen incorporation on PMOS negative bias temperature instability in ultra-thin oxy-nitrides—L. Duong, V. Gopinath, S. Prasad, J. Lin, E. Li, and V. Hornback, LSI Logic Corporation
P11 Effect of new inter-layer-dielectric on plasma charging damage in 0.13 µm dual gate oxide— W.H. Lu, L.H. Ko, K.L.Y. Andrew, and K.F. Lo, Chartered Semiconductor Mfg. Ltd.
P12 Impact of junction temperature on microelectronic device reliability and considerations for space applications—M. White, M. Cooper, and Y. Chen, JPL
P13 Massively parallel GOI test—T.K. Ng, K.F. Lo, B.B. Jie and Y. Andrew, Chartered Semiconductor Mfg. Ltd.
P14 Reliability results on a 0.25 micron aluminum backend with a TiN Liner—L. Westergard, M. Nelson, B. Williams, and J. Prasad, AMI Semiconductor
P15 HCI lifetime enhancement by PLDD implant energy optimization of Pch MOSFET in 0.13 µm CMOS technology—L. Hyeokjae, E. Quek, Y. Andrew and M. Fakhrul Karim, Chartered Semiconductor Mfg. Ltd.
P16 Similarity of Pre-Breakdown Leakage Current Fluctuations for p- and nMOSFETs—J.C. Reiner, EMPA
contact via email
Technical Poster Session Chair IRW 2003
otherwise
William R. Tonti
IBM Engineering and Technical Services
1000 River Street
Essex Junction, VT 05452
Phone: +1 802 769 6561
Fax: +1 802 769 6567