The poster session of the IRW 2004 will showcase three types of posters:
Refereed posters, Open posters and Walk-in Posters:
Walk-in Posters are last minute posters.
Bring your poster directly to IRW
and have the poster session chair assign a poster board to you.
You are also invited to submit a two-page maximum manuscript of your poster
presentation for inclusion in the IRW 2004 Final Report
(see Milestones below for due date).
Note: All posters and poster manuscripts must comply with the guidelines given below.
Poster Preparation:
If you are presenting a Refereed or Open poster, a display board will be reserved for you. The display board area is 32" × 40" or 81 cm × 100 cm. Your work should be in Landscape format on 8½ × 11" or A4 paper with a maximum of 12 pages. Choose a simple, bold font, readable on hard copy from a distance of 2 meters (20-pt. size). Color is acceptable. Please strive for simplicity and clarity in your poster pages. Do not include Logos or names of your employer or university on any of the viewgraphs, except for the title viewgraph.
Manuscript/Abstract Preparation:
Details for preparation of the abstract for inclusion in the IRW Final Report can be found on the IRW Author Instruction webpage. Milestones for preparation of the abstract can be found below.
In the following table, you will find a short list of critical milestones for preparing your 2004 IRW Poster presentation. In order to complete the job, we need your help in adhering to the deadlines below.
| DATE | MILESTONES | REMARKS |
| 7/30/04 | E-mail Poster Program Chair (Bill Knowlton) accepting or declining invitation to present a refereed poster. |
Confirmation needed (refereed posters only) |
| 9/28/04 | Draft Summary to the Poster Program Chair (Bill Knowlton). |
Your Mentor will contact you. (refereed posters only). |
| 10/13/04 | Open Posters: reserve poster display board. | Contact poster Program Chair (Bill Knowlton) |
| 10/18/04 | Submit final manuscript draft and signed IEEE Copyright Form | Give to Poster Program Chair (Bill Knowlton) at the conference. (see instructions for preparation details) |
We encourage presentation of your latest ideas and newest results on technical projects or issues by accepting your poster upon your arrival at the workshop (see the Technical Poster Chair). If possible, please indicate your intention to bring a poster by reserving a poster display board in the space provided on the registration form or/and sending an e-mail to the Technical Poster Chair by 10/13/04.
Poster Presentation in Final Report Example (pdf)
IEEE Copyright Form
P1 Influence of Dopants on PolySilicon Capacitor Oxide Failure—Janet M. Towner, John J. Naughton, AMI Semiconductor
P2 Gate Oxide Integrity Improvement by Optimising Poly Deposition Process— Tze Kiong Ng, Andrew Yap, Hiau Tong Chan, Keng Foo Lo, Purakh Raj Verma, Chartered
P3 Pseudo-Progressive Breakdown of Ultra-Thin Nitrided Gate Oxide—Joachim Reiner, EMPA
P4 An Innovative Multi-Via Test Structure for Wafer-Level Isothermal Electromigration—Summer Tseng, Wei-Ting Kary Chien, Willings Wang, SMIC
P5 The Study of Sputtered RF Ta on the PID in Cu Dual Damascene Technology —Wen Hui Lu, Kim Keng Teo, Chaw Sing Ho, Kin Leong Yap Andrew, Keng Foo Lo, Chartered
P6 DF-RQA Practice for SoC—Haim Marom, Freescale
P7 Enhanced Hot Carrier Degradation in Deep Submicron NMOSFET and PMOSFET— Liang-Nio Lie, Jaap Bisschop, Dan Oliver, Margaret Redmond, Philips
P8 Process Dependence of Hot Carrier Degradation in PMOSFETS—Erhong Li, Sharad Prasad, Lesly Duong, LSI Logic
P9 X-rays Total Dose Radiation Effect on nMOSFET's ESD Reliability—Luo Hongwei, En yunfei, Zhu Zhangming, Xidian and Guangzhou Universities
P10 Circuit and Silicide Impact on the Correlation Between TLP and ESD (HBM and MM)—S.C. Huang, J.H. Lee, S.C. Lee, K.M. Chen, M.H. Song, C. Y. Chiang, M.C. Chang, TSMC
P11 DRAM Standby Current Failure: The Influence of Hot Carrier Degradation on Voltage Level-up Shifter Circuit—K. Lee, J.Y.Seo, J.W.Jung, G.J.Jung, J.H.Lee, S.J.Hwang, C.K.Yoon, Samsung
P12 Reliability Issues in Advanced Monolithic Embedded High Voltage CMOS Technologies—Guoqiao Tao, Philips
P13 Improvement of Spacer Particle Induced Reliability Failures—Summer Tseng, Kary Chien, Vivi Ruan, Scott Liao, SMIC
P14 Procedure for Quantitative fWLR Monitoring of Gate Dielectric Reliability—Rolf-Peter Vollertsen, Infineon Technologies
contact via email
Technical Poster Session Chair IRW 2004
otherwise:
William B. Knowlton (bknowlton@boisestate.edu)
Boise State University
Department of Electrical & Computer Engineering
1910 University Dr.
Boise, ID 83725-2075
Phone: +1 208 426 5705
Fax: +1 208 426 2470
Technical Poster Session Vice-Chair IRW 2004
Sharad Prasad (sharad@lsil.com)
LSI Logic
1621 Barber Lane
Milpitas, CA 95035
Phone: 408-433-7446
Fax: +1 208 426 2470