DISCUSSION GROUP TOPICS

GROUP TOPICMODERATORS
1) Gate Oxide Reliability Andreas Kerber, Infineon Technologies
John Suehle, NIST
2) NBTI Anand Krishnan, Texas Instruments
Erhong Li, LSI Logic
3) Interconnect Reliability Tim Sullivan, IBM Microelectronics
Xavier Federspiel, Philips
4) Product Reliability Andrew Turner, IBM Microelectronics
Yue Kuo, Texas A&M Univ

Abstracts and Questionnaires
Please copy the questionnaire of the discussion topic(s) you are interested in into a WORD file, complete the questionnaire(s) and e-mail the file to sylvie.bruyere@st.com, who will forward it to the appropriate moderator(s). Thanks for helping to improve the efficiency of the IRW Discussion Groups.

1) Gate Oxide Reliability

Moderators: Andreas Kerber, Infineon Technologies and John Suehle, NIST

CMOS scaling beyond the 90 nm node requires the reduction of the gate dielectric thickness down to an Equivalent Oxide Thickness (EOT) of ~ 1 nm which will either be realized with SiON or high-k gate dielectrics. Both strategies, further downscaling of SiON gate dielectrics or the introduction of high-k dielectrics, bring various critical reliability challenges with it which need to be tackled in order to meet the stringent reliability requirements of future CMOS technologies. In this discussion group some of the future gate oxide reliability challenges for either SiON or high-k gate dielectrics are going to be addressed. Therefore the following questionnaire has been compiled which should be completed and returned by interested attendees prior to the conference to one of the moderators. We are looking forward to an interesting and stimulating discussion on the gate oxide reliability challenges.

Gate oxide reliability issues for SiON dielectrics:

  1. Is softbreakdown of the gate dielectric still an appropriate failure mode for the reliability assessment of MOSFETs in future CMOS technologies?

      • Yes

      • No

  2. Is the progressive breakdown a suitable failure criterion for future CMOS technologies?

      • Yes

        • What would be the underlying statistical model (Weibull, Log-normal, … )

          • Weibull.

          • Log-normal.

          • Other ………………

          • We do not know enough about progressive breakdown yet.

      • No

  3. Has the softbreakdown / progressive breakdown an impact on the circuit functionality and performance?

      • Yes

        • Does current limitation during successive breakdown play a role?

          • Yes

          • No

        • Does the logic design (static, dynamic, …) have an impact?

          • Yes

          • No

      • No

     

Gate oxide reliability issues for high-k dielectrics:
  1. When do you expect high-k gate dielectrics being introduced?
    • 65 nm node
    • 45 nm node
    • In a later technology node
    • Never, high–k is just an academic exercise.
  2. Is the reliability methodology of conventional SiO2 / SiON based gate dielectrics applicable to high-k gate dielectrics?
    • Yes
    • No
      • What improvements / adjustments are required?

    ……………………………………………………………………

    ……………………………………………………………………
  3. What is the most critical challenge for the reliability assessment of MOS devices with high-k gate dielectrics? (check all that apply)
    • Methodology
    • Modelling
    • Conduction mechanism (TAT, P-F conduction, Schottky emission, … )
    • Dielectric breakdown (Soft versus hard)
    • Stress Induced Leakage Current (SILC)
    • Charge trapping
    • BTS (NBTI, PBTI)
    • Noise (1/f, …)
    • Defect density
    • Others …………………………
  4. Are the degradation models known from SiO2 applicable to high-k gate dielectrics?
    • Yes, which physical models are valid? (check all that apply)
          • Anode hole injection
          • Hydrogen release,
          • Carrier energy
          • Oxide field
    • No, the wear-out mechanism for high-k is completely different than SiO2.
  5. What voltage acceleration for TDDB is applicable?

    6.
  6. What conduction mechanism is dominant in high-k dielectrics?
    7.
  7. Does the gate electrode have an influence on the reliability of high-k dielectrics?
    8.

2) NBTI

Moderator: Anand Krishnan, Texas Instruments and Erhong Li, LSI Logic

PMOS negative bias temperature instability (NBTI) has become one of the key reliability concerns in recent years, resulting in a significant activity in this area. Significant discrepancies exist among the different reports even on key aspects of this phenomenon, such as time, temperature and field dependency. The discussion group will focus on the various facets of the NBTI phenomenon, including-
  • Nature of the defect (s) causing NBTI
  • Models seeking to explain observed time/temperature/field dependencies
  • Significance of charge trapping during NBTI
  • Process impact - The role of nitrogen and fluorine
  • Recovery and Frequency dependence

Name (Optional) :

Company (Optional) :

Topics of Interest: Please rank the top 3 topics of interest, with 1 being the highest

TOPIC

RANK

Nature of Precursor/defect

 

NBTI Kinetics: Time, temperature and field dependencies

 

Models for NBTI: Charge trapping, fixed charge creation, Interface states

 

Measurement aspects: Choice of device, parameter, lifetime criterion

 

Recovery and frequency dependence

 

Nitridation impact

 

Role of hydrogen, water and BEOL

 

Statistical aspects of NBTI

 

NBTI and its relation to TDDB

 

Compact, TCAD and SPICE Models

 

The following questions pertain to NBTI in your specific organization. The results of this survey will be collated and published along with the summary of the discussions.

TOPIC

YES

NO

ORGANIZATION

 

 

NBTI is considered a critical issue for qualification in my organization

 

 

We have a team to address NBTI at the transistor level

 

 

We have run splits to identify process knobs for NBTI lifetime enhancement

 

 

We have _ _ _ _ people working full time on NBTI

 

 

DEVICE

 

 

We use power law time dependency for lifetime projections

 

 

We observe channel length dependence of NBTI

 

 

We observe channel width dependence of NBTI

 

 

We have seen significant FEOL impact on NBTI lifetime

 

 

We have seen significant BEOL impact on NBTI lifetime

 

 

NBTI is a bigger problem for I/O devices than core devices

 

 

We have an IDSAT based spec.

 

 

We have a VT based spec.

 

 

Our spec. value is same for different dielectric thicknesses

 

 

RECOVERY & AC EFFECTS

 

 

We make AC measurements to assess lifetimes

 

 

We utilize the recovery phenomenon to our benefit

 

 

We utilize the AC lifetime enhancement to our benefit

 

 

We use recovery after burn-in to our advantage

 

 

We have a guard banding methodology in place for NBTI

 

 

We have models to account for the statistical variations in NBTI

 

 

CIRCUITS

 

 

We have SPICE models to account for NBTI degradation during operation

 

 

NBTI is a concern for digital circuits

 

 

NBTI is a concern for analog circuits

 

 

MISCELLANIOUS

 

 

We have seen significant stress impact on NBTI

 

 

Devices with SiGe show higher NBTI

 

 

Multigate transistors show higher NBTI

 

 

We have a FIT rate for NBTI

 

 

3) Interconnect Reliability

Moderator: Tim Sullivan, IBM Microelectronics and Xavier Federspiel, Philips

The announcement for the IRW Interconnect Discussion group for 1998 is shown below. This year's Interconnect Discussion Group will begin with a look back over the last 6 years, to see what we anticipated and what we missed.

IRW Interconnect Discussion Group, 1998

To meet anticipated requirements over the next 15 years, the U.S. National Technology Roadmap for Semiconductors charts an aggressive path for evolution of current interconnect technology. Insertion of new interconnect materials (Cu as the primary conductor, with refractory metal liners) is already underway, and, to stay on the NTRS timeline, insertion of new dielectric materials will be required in the near future. With interconnect lengths of kilometers per circuit, minimum linewidths shrinking below 100nm, the number of metallization levels moving toward 10, and the use of an interconnect metal which must be fully isolated from the dielectric, enormous reliability challenges must be met during a period of rapid development of new materials and processes. The goals of this discussion group will be to identify areas of greatest concern, and share lessons learned, and anticipated needs.

    Specific discussion topics will include:
  • Can the same reliability approaches that were used for Al be applied to Cu?
  • Is electromigration-induced failure still an issue for Cu-based alloys?
    • What are the new design rules?
    • Are new design strategies enabled?
    • Are existing design strategies still OK?
  • How do liners for Cu affect electromigration?
  • Are there reliability issues with the liners themselves?
    • How easy is it to insure that liners are continuous everywhere on a kilometer of interconnect?
    • Are there wear-out failure mechanisms for liners, such as cracking due to thermal cycling?
    • How can liner reliability be assessed?
  • Are there new processing-related defects arising from Cu-based technologies which lead to reliability issues?
    • How important is Cu adhesion?
    • How significant are the differences in Cu deposition techniques?
  • What are the implications of dual damascene vias?
    • Will liner integrity in vias be a problem?
    • Will aspect ratio uniformity be maintained ?
    • Will stress become an issue?
  • How will the mechanical and thermal properties of Low-K dielectrics affect reliability?
  • Are there other properties of Cu or Low-K, different from Al and SiO2, which could bring in unanticipated reliability challenges?

4) Product Reliability

Moderator: Andrew Turner, IBM Microelectronics and Yue Kuo, Texas A&M Univ

As chip integration increases and SOC architectures gain wider implementation, the reliability per device will need to increase accordingly. Furthermore, as our world becomes further dependent on microelectronic products, the expectation of reliability will increase. An example is the drive-by-wire active braking systems in automobiles.

The most powerful method in reducing the module level defect population has been burn-in, but due to rising costs and increasing power densities novel approaches must be used to extend the feasibility of manufacturing burn-in. The discussion will include (but not be limited to) product reliability, early fails and defects, Burn-In and it's reduction, useful lifetime targets and conditions (e.g. the operation temperature of a cellular phone is never over 40°C, because then you cannot touch it anymore).
  1. As lithographic dimensions decrease, are the fail defect types changing that which would affect the failure rate improvement of burn-in?
    1. Has this shifted the ratio of short type defects to opens?
      • Yes
      • No
    2. Are intrinsic mechanisms (NBTI, hot e-, TDDB, EM) driving more or less burn-in fallout than traditionally observed?
      • More
      • Less
      • No change
    3. From a product perspective, have the impact of intrinsic mechanisms and defect types increased or decreased the observed acceleration factors?
      • Increase
      • Decrease
      • No change
    4. How has this impacted the improvement provided to field reliability by burn-in?
      • Burn-in is more effective
      • Burn-in is less effective
    5. Is thermal cycling considered a significant proportion of the total chip failure rate?
      • Yes
      • No
  2. What drives the conditions applied during burn-in?
    1. Is burn-in temperature based on physical limitation of device, package, or tool?
      • Device
      • Package
      • Tool
      • Other
    2. Is burn-in voltage based on device or tool limitations?
      • Device
      • Tool
      • Other
    3. Is frequency based on test, tool, or device limitations?
      • Test
      • Tool
      • Device
      • Other
  3. What drives the frequency at which burn-in is performed?
    1. Has applied frequency of burn-in patterns been verified to provide any improvement in acceleration?
      • Yes
      • No
    2. Has it been shown to decrease parametric degradation?
      • Yes
      • No
  4. Is the industry moving toward in-situ testing in order to make up for the increased challenges of providing high reliability while facing new defect types?
    • Yes
    • No
    1. Does in-situ testing affect the ability to reduce SPQL / early life fails?
      • Yes
      • No
    2. Is at-speed test used for in-situ monitoring?
      • Yes
      • No
  5. What is the main indicator for burn-in reduction?
    • Internal product reliability monitoring
    • Internal test site monitoring
    • Customer reliability feedback
    • Wafer test results
  6. What level of information is required from the customer in terms of use conditions which feed into the reliability model?
    • Min/Max voltage
    • Min/Max temperature
    • Ambient thermal profile
    • System thermal profile of chip (e.g. fan/cooling settings)
    • Power-on-hours
    • On-off cycles
    • Power supply tolerance
    • Performance/Power tuning implementation
    1. Which of these parameters are set by application or chip specification?
    2. From the above information, how is range data used?
      • Worse case of parameter
      • Nominal case
      • Statistical distribution (if information exists)
  7. Given the increasing challenges in providing inexpensive methods to increase customers reliability, will the future require the most progress in:
    • Process development
    • Test screen development
    • Acceleration types screen development (burn-in, voltage bump, etc)
    • Chip level circuit healing techniques
    • System level methods (redundancy, etc)

Another discussion group (DG) may be added if there is sufficient interest in a certain topic. If you desire to discuss a certain topic please indicate on the registration form and also contact Sylvie Bruyere (DG Chair) sylvie.bruyere@st.com, especially if you would volunteer to moderate the discussion of that topic. If we do not have enough people interested in a newly proposed topic it is still possible to form a special interest group (SIG). Sylvie will let you know whether an additionally proposed topic has potential to become DG or SIG.