Tutorials A:

Characterization of Alternative Gate Dielectrics Using Electrical C-V and I-V Measurements - Khaled Ahmed, Applied Materials

Continued miniaturization of CMOS devices beyond 90 nm technology generation requires gate oxides thinner than 12Å. In this thickness range, alternative materials such as Si-Oxynitrides and HfO₂ have been pursued in order to alleviate power dissipation related to quantum mechanical gate tunneling current. Achieving reliability characteristics that closely match, or exceed, those of SiO₂ is one of the most important challenges facing the development of these materials which show new reliability phenomena. The understanding of these phenomena requires accurate knowledge of the device electrophysical parameters such as equivalent oxide thickness, dielectric constant, tunneling effective mass and barrier height, and interface and bulk trap density. In this tutorial, issues related to the characterization of alternative gate dielectrics based on electrical C-V and I-V measurements are discussed.

High-k dielectrics: Materials Physics, Instabilities, Defects, and Reliability- John Conley, Sharp Labs

Due to continued device scaling, there is an impending need for a high dielectric constant replacement for SiO₂. However, despite the massive amount of effort over the last several years, the future of high-k is still uncertain. Several unsolved problems still remain, including charge trapping induced Vt instability, mobility degradation, and reliability. This tutorial will focus primarily on HfO₂ and will include a brief review of the materials physics of high-k films as well as aspects of film deposition (atomic layer > -> ALD), material characteristics, interfacial issues, and reliability. Recent work to identify atomic scale defects and their roles in high-k thin film / Si systems will be reviewed. Reference to the current understanding in SiO₂ will be included.

Tutorials B:

Gate Oxide Lifetime Limited by Pre- and Post-Breakdown Degradation- Frederic Monsieur, ST Microelectronics

The aggressive gate oxide thickness scaling and the overdriven nominal gate voltages make gate oxide lifetime requirements less and less fulfilled. If the physics of the gate oxide wear-out let very few chance to make ultimate dielectrics reliable, in parallel a second chance is provided by the soft manifestation of the failure.

Actually, when the oxide breakdown is triggered a very low and tolerable level of gate current may be induced enabling the device and then the circuit to continue to operate properly. For all that, the breakdown induced current increases progressively with circuit operation making this lucky situation limited in time. In addition other breakdowns may occur in this period and bring the circuit to its final breakdown.

As a result this tutorial will be divided in two parts. In the first one, we will try to understand how, why and when the dielectric experiences its first breakdown. In the second part, we will review the very recent results concerned with the post-breakdown degradation that leads to the circuit breakdown.

If the physics related to the pre- or post-breakdown degradation is reviewed, the statistical aspects are deeply treated and we will discuss their relative importance in the circuit lifetime prediction.

Reliability of a-Si TFTs From Processing to Device Issues- Yue Kuo, Texas A&M Univ.

Thin film transistors (TFTs) are one of the hottest solid state technologies in the past decade. The TFT based liquid crystal displays (LCDs) has a predicated annual market value of over $50B in 2004. TFTs are also applicable in many other electronic, optoelectronic, medical, and sensor products. In this talk, we are going to review the TFT technology with emphasis on reliability issues related to fabrication processes, device physics, and applications.

Tutorials C:

Electromigration Reliability of Cu/Low k Interconnects - Martin Gall, Freescale / Paul S. Ho, U.T. Austin

The distinct EM behavior of Cu Interconnects induced by the dual-damascene structure and process will be first discussed and compared with Al interconnects. The statistical approach used to study EM failure statistics and threshold current density-length products will be presented first for Cu/oxide structures, and then compared with Cu/low k structures. The impact of weak thermomechanical properties of low k dielectrics on EM reliability will be assessed based on the concept of effective elastic modulus. Finally the recent development using interfacial layer to improve Cu EM reliability will be discussed.

Stress-Induced Voiding and Related Behavior in Advanced Microelectronics Metallization - Tim D. Sullivan, IBM Microelectronics

Stress-induced voiding was first observed in the late 80's in chips with aluminum metallization and with minimum line widths as large as 3 um. Since that time, Al-based metallization has evolved considerably, and for many applications and technologies, has been replaced by Cu metallization. Although Cu should be considerably more resistant to stress-induced voiding than Al metallization, when Cu metallization is subjected to the same thermal stresses that produced voiding in Al, sometimes voids appear in the Cu and cause failure. This tutorial will review the description of stress voiding in Al and will discuss how that relates to the voiding behavior observed in Cu, and how elemental, microstructural and environmental (processing and integration) properties of Cu and Al modify the voiding behavior.

Tutorials D:

NBTI: What We Know and What We Need to Know- Greg Massey, IBM Microelectronics

In advanced CMOS technologies, the Negative Bias Temperature Instability (NBTI) phenomenon in pMOSFETs is a major reliability concern as well as a limiting factor in future device scaling. Recently, much effort has been expended to further the basic understanding of this mechanism. This tutorial will give an overview of the physics of NBTI. Discussion will include such topics as the impact of NBTI on the observed changes in the device characteristics as well as the impact of gate oxide processes on the physics of NBTI. Current experimental results exploring various NBTI effects such as frequency dependence and relaxation will also be discussed. Since some of the recent work on the various NBTI effects seems contradictory, focus will be placed on highlighting our current understanding, our open questions and our future challenges.

Modeling NBTI: Kinetics to Circuits- Anand Krishnan, Texas Instruments

Negative bias temperature instability (NBTI) has become one of the dominant circuit degradation mechanisms in recent years. In this report, recent work in modeling this phenomenon is summarized. Firstly, scaling trends that have caused NBTI to become significant are discussed. Then, models explaining the degradation kinetics, including acceleration parameters such as temperature and voltage are elucidated. This is followed by a description of the nature of defects produced by NBTI. In the final section, the circuit impact of NBTI is demonstrated through data as well as simulations