Microelectronics circuit chips using advanced manufacturing techniques are producing metallization line widths on the order of 0.2 micron or less. For a processor chip 25 mm square with 10 levels of metal and 30% coverage per level, this represents total line lengths in the neighborhood of a few kilometers per chip, and hundreds of millions of interlevel connections (vias). In addition to the usual wear out mechanisms electromigration and stress voiding, we can now add mechanical breakage during thermal cycling and corrosion to the list as Low-K dielectrics replace the more traditional SiO₂.

The cooling demands alone, both for operating conditions and for testing, are becoming progressively more prohibitive. Local hot spots on the chips are driving the use of more sophisticated modeling techniques, aimed at redistributing the thermal load. This problem is exacerbated by the use of Low K dielectrics, which also have lower thermal conductivities. Local hot spots cause enhanced acceleration of wear out mechanisms, requiring a more detailed view of chip operating temperature.

This year’s Interconnect Discussion Group invites attendees to share concerns, insights and approaches to these challenges. Bring your stories, anxieties, victories, wisdom, knowledge, questions and confusion to toss in the pot and see what kind of a brew we can concoct.

NOTE:  If you plan on attending, please download the questionnaire, complete it, and return to ynelson@qualcomm.com by 10/10/05.  Thank you for helping to improve the efficiency of the IRW discussion groups.

Questionnaire (as a WORD document) (as html)

Interconnects Discussion Group—Questionniare

General Topics

1. Technology Needs and Limits
1. Will technologies continue to scale down metal dimensions? Limits?
2. Is electromigration a fundamental technology limitation in advanced circuits?
1. In special circumstances only, or globally
2. Solutions?
3. What are the limitations of Low-K dielectrics?
1. Mechanical, thermal properties
2. Chemical properties (like moisture uptake)
4. Will stress voiding continue to be a concern?
2. Data Analysis
1. Are present statistical methods indefinitely extendable?
2. Are they valid?
3. Stress voiding in Cu/Low-K
1. Specialized structures, necessity and validity
2. How to bridge to product
3. Failure statistics
4. Electromigration stress limitations (current and temperature)
1. Stress Current Selection
1. How high Joule heating is acceptable ?
1. Dependencies (geometry, materials (metal, ILD), wafer/pkg. stress)?
2. How high a current density is acceptable ?
1. Dependencies (as above)?
3. Are 3 currents enough for n-value extraction?
2. Stress Temperature selection
1. How high line temperature is acceptable ?
1. Dependencies (geometry, materials (meta, ILD), wafer/pkg. stress)?
2. Are 3 temperatures enough for Ea value extraction?
3. How are test structures (ASTM, NIST, FSA, Jedec designs) chosen?
4. Can you test for nominal dimensions and or other sizes?
5. PCM for metallization ?
1. Wafer level (Isothermal, Sweat, other)?
2. Package level (possible to make faster?)