General Topics

1. Technology Needs and Limits
1. Will technologies continue to scale down metal dimensions? Limits?
2. Is electromigration a fundamental technology limitation in advanced circuits?
1. In special circumstances only, or globally
2. Solutions?
3. What are the limitations of Low-K dielectrics?
1. Mechanical, thermal properties
2. Chemical properties (like moisture uptake)
4. Will stress voiding continue to be a concern?
2. Data Analysis
1. Are present statistical methods indefinitely extendable?
2. Are they valid?
3. Stress voiding in Cu/Low-K
1. Specialized structures, necessity and validity
2. How to bridge to product
3. Failure statistics
4. Electromigration stress limitations (current and temperature)
1. Stress Current Selection
1. How high Joule heating is acceptable ?
1. Dependencies (geometry, materials (metal, ILD), wafer/pkg. stress)?
2. How high a current density is acceptable ?
1. Dependencies (as above)?
3. Are 3 currents enough for n-value extraction?
2. Stress Temperature selection
1. How high line temperature is acceptable ?
1. Dependencies (geometry, materials (meta, ILD), wafer/pkg. stress)?
2. Are 3 temperatures enough for Ea value extraction?
3. How are test structures (ASTM, NIST, FSA, Jedec designs) chosen?
4. Can you test for nominal dimensions and or other sizes?
5. PCM for metallization ?
1. Wafer level (Isothermal, Sweat, other)?
2. Package level (possible to make faster?)