Gate Oxide / High-k Reliability Discussion Group Questionnaire

 

Technologies

 

  1. Technology Needs and Limits
    1. Will technologies continue to scale down electrical oxide thickness? Limits?
    2. What are the limitations of gate dielectrics?
      1. Leakage
      2. Reliability
      3. When do you expect high-k gate dielectrics being introduced?

      o 45 nm node

      o In a later technology node

      o Never, high–k is just an academic exercise.

    3. Will technologies continue with poly gate?
    4. When do you expect metal gate being introduced in CMOS technologies?

o 45 nm node

o In a later technology node

o Never, metal gate is just an academic exercise.

 

SiO2/SiON

 

II. Which degradation models dominate the SiO2/SiON breakdown?

o Anode hole injection

o Hydrogen Release

o Multi-vibrational hydrogen release

o Carrier energy

o Oxide field

 

III. Do you use lifetime extension for TDDB (oxide below 14Å)?

o Yes

o No

a. Which methodology do you use?

o Power consumption Max

o X breakdown on a same transistors

o X breakdown on the circuits

o Shift of transistors characteristics (Vt, Ion, Ioff,…)

o Others

 

Metal Gate

 

IV Do you think that, with metal gate, the oxide breakdown still allows the lifetime extension?

o Yes

o No

 

V Do you think that the oxide breakdown with metal gate represents a metal gate integration showstopper?

o Yes

o No

 

VI. Are the degradation models known from Poly/SiO2 applicable to Metal/SiO2?

o Yes, which physical models are valid? (check all that apply)

o Anode hole injection

o Hydrogen release

o Multi-vibrational hydrogen release

o Carrier energy

o Oxide field

 

VII. What voltage acceleration for TDDB is applicable with metal gate?

o exp(1/V)

o exp (a V)

o Vn (power law)

o Some other dependence

 

VIII. What is the most critical challenge for the reliability assessment of MOS devices with metal gate? (check all that apply)

o Methodology

o Dielectric breakdown (Soft versus hard)

o Stress Induced Leakage Current (SILC)

o Charge trapping

o NBTI PBTI

o Noise (1/f, …)

o Defect density

o Others …………………………

 

 

 

High-K dielectrics

 

IX. Is the reliability methodology of conventional SiO2 / SiON based gate dielectrics applicable to high-k gate dielectrics?

o Yes

o No

What improvements / adjustments are required?

 

X. Are the degradation models known from SiO2 applicable to high-k gate dielectrics?

o Yes, which physical models are valid? (check all that apply)

o Anode hole injection

o Hydrogen release

o Multi-vibrational hydrogen release

o Carrier energy

o Oxide field

 

XI. What voltage acceleration for TDDB is applicable with metal gate?

o exp(b/V)

o exp(aV)

o Vn (power law)

o Some other dependence

 

XII. What is the most critical challenge for the reliability assessment of MOS devices with high-k gate dielectrics? (check all that apply)

o Methodology

o Dielectric breakdown (Soft versus hard)

o Stress Induced Leakage Current (SILC)

o Charge trapping

o NBTI PBTI

o Noise (1/f, …)

o Defect density

o Others …………………………