1) Gate Oxide / High-k Reliability
Discussion Group
Moderators: Guillaume Ribes, STMicro
and John Suehle, NIST
CMOS scaling beyond
the 45 nm node requires the reduction of the gate dielectric thickness down to
an Equivalent Oxide Thickness (EOT) of ~1 nm which will either be realized with
SiON or high-k gate dielectrics. In addition, a local
environment change such as the future integration of the metal gate, can significantly change the oxide reliability (such as
progressiveness, NBTI). These different options, such as further downscaling of
SiON gate dielectrics and the introduction of new
gate materials, bring various critical reliability challenges with it which
need to be tackled in order to meet reliability requirements of future CMOS
technologies. In this discussion group some of the future gate oxide
reliability challenges for both SiON and high-k gate
dielectrics will be addressed. The impact of new gate materials on gate oxide
reliability will be also discussed.
NOTE: If you plan on attending, please download the
questionnaire, complete it, and return to ynelson@qualcomm.com by 10/10/05. Thank you for helping to improve the
efficiency of the IRW discussion groups.
Questionnaire (as a WORD document) (as html)
Gate Oxide / High-k Reliability Discussion Group Questionnaire
Technologies
o 45 nm node
o In a later technology node
o Never, high–k is just an academic exercise.
o 45 nm node
o In a later technology node
o Never, metal gate is just an academic exercise.
SiO2/SiON
II. Which degradation models dominate the SiO2/SiON breakdown?
o Anode hole injection
o Hydrogen Release
o Multi-vibrational hydrogen release
o Carrier energy
o Oxide field
III. Do you use lifetime extension for TDDB (oxide below 14Å)?
o Yes
o No
a. Which methodology do you use?
o Power consumption Max
o X breakdown on a same transistors
o X breakdown on the circuits
o Shift of transistors characteristics (Vt, Ion, Ioff,…)
o Others
Metal Gate
IV Do you think that, with metal gate, the oxide breakdown still allows the lifetime extension?
o Yes
o No
V Do you think that the oxide breakdown with metal gate represents a metal gate integration showstopper?
o Yes
o No
VI. Are the degradation models known from Poly/SiO2 applicable to Metal/SiO2?
o Yes, which physical models are valid? (check all that apply)
o Anode hole injection
o Hydrogen release
o Multi-vibrational hydrogen release
o Carrier energy
o Oxide field
VII. What voltage acceleration for TDDB is applicable with metal gate?
o exp(1/V)
o exp (a V)
o Vn (power law)
o Some other dependence
VIII. What is the most critical challenge for the reliability assessment of MOS devices with metal gate? (check all that apply)
o Methodology
o Dielectric breakdown (Soft versus hard)
o Stress Induced Leakage Current (SILC)
o Charge trapping
o NBTI PBTI
o Noise (1/f, …)
o Defect density
o Others …………………………
High-K dielectrics
IX. Is the reliability methodology of conventional SiO2 / SiON based gate dielectrics applicable to high-k gate dielectrics?
o Yes
o No
What improvements / adjustments are required?
X. Are the degradation models known from SiO2 applicable to high-k gate dielectrics?
o Yes, which physical models are valid? (check all that apply)
o Anode hole injection
o Hydrogen release
o Multi-vibrational hydrogen release
o Carrier energy
o Oxide field
XI. What voltage acceleration for TDDB is applicable with metal gate?
o exp(b/V)
o exp(aV)
o Vn (power law)
o Some other dependence
XII. What is the most critical challenge for the reliability assessment of MOS devices with high-k gate dielectrics? (check all that apply)
o Methodology
o Dielectric breakdown (Soft versus hard)
o Stress Induced Leakage Current (SILC)
o Charge trapping
o NBTI PBTI
o Noise (1/f, …)
o Defect density
o Others …………………………