2005 IRW Poster Session
Information
The poster session of the
IRW 2005 will showcase three types of posters:
1.
Refereed Posters will be selected from submitted abstracts by the
beginning of August and the authors notified. A list
of the authors and titles will appear below. Check this page for
updates. A display board is
automatically reserved for you. You are
invited to submit a four-page (maximum) manuscript of your poster presentation
for inclusion in the 2005 IRW Final Report (see Milestones
below for due date). This is a great
opportunity for you to share your work with your peers.
2.
Open posters provide a forum for all attendees to communicate and discuss
their ideas and newest results on technical projects or issues. Please indicate
your intention to bring a poster in the space provided on the registration form
or/and by sending an e-mail to the Poster
Session Chair. A display board will
be reserved for you. In addition, you
are invited to submit a two-page (maximum) manuscript of your poster
presentation for inclusion in the 2005 IRW Final Report (see Milestones below for due date).
3.
Walk-in
Posters are last minute posters.
Bring your poster directly to IRW and have the Poster Session Chair assign a
display board to you. You are also invited to submit a two-page (maximum)
manuscript of your poster presentation for inclusion in the IRW 2005 Final
Report (see Milestones below for due date).
Note:
All posters and poster manuscripts must comply with the guidelines below:
Poster Preparation:
Mechanics
Technical/Scientific
Organization
Manuscript/Abstract Preparation:
Details for preparation of
the abstract for inclusion in the IRW Final Report can be found on the IRW Author Instruction webpage.
In the following table, you will find a short list of critical milestones for preparing your 2005 IRW Poster presentation. In order to complete the job, we need your help in adhering to the deadlines below.
|
DATE |
MILESTONES |
REMARKS |
|
|
E-mail Poster Program Chair (Pat Lenahan) accepting or declining invitation to present a refereed poster. |
Confirmation needed |
|
|
Draft Summary of poster due to the Poster Sessions Chair. |
Your |
|
|
Open Posters: reserve poster display board. |
Contact Poster Sessions Chair |
|
|
Submit final manuscript and signed IEEE Copyright Form |
Give to Poster Sessions Chair (Pat Lenahan) at the conference (see IRW Author Instruction webpage for details). |
We encourage presentation of
your latest ideas and newest results on technical projects or issues by
accepting your poster upon your arrival at the workshop (track down the Poster
Sessions Chair). However to facilitate
planning, if possible, please indicate your intention to bring a poster in the
space provided on the registration form or/and sending an e-mail to the
Technical Poster Chair by
Downloads
Poster
Presentation in Final Report Example (pdf)
Acrobat version of the IEEE
Copyright Form
P1 Testing methodology for lifetime extrapolation of pzt capacitorsE.
Bouyssou1,2, S.
Bruyère2, G.
Guégan2, C.
Anceau2, A.
Agostini1,2, R. Jérisian1 P2 Efficient fWLR inline monitoring of hot carrier reliability by means of
one simple, comprehensive parameterR. Vollertsen, H. Nielen, Infineon Technologies
P3 An investigation on stacked NMOSFET with different poly-gates bias
conditions under ESD stress in 0.13µm CMOS tolerant I/O circuitC.-Y. Huang, G.
Chen, United Microelectronics Corp.
P4 Impact of NBTI-driven parameter degradation on lifetime of a 90nm
p-MOSFETR. Wittmann1, H.
Puchner2, L. Hinh2, H.
Ceric1, A. Gehring3,
S. Selberherr1 P5 Hot carrier effect on CMOS class e power amplifiersE. Xiao, UT Arlington
P6 The novel mechanism of temperature effect in ultra-thin oxide breakdown
J. Shieh, T.-K. Kang, C.-L. Lin, O. Lo, J.-P. Chen, K.C. Su, UMC
P7 Impact of device scaling on deep sub-micron transistor reliability - A study
of reliability trends using SRAMM.
White1,2, Z. Gur2, M.
Talmor2, B. Huang2,J.
Qin2, X. Li2, X.
Zhang2, Y. Chen1, D.
Nguyen1, J. Bernstein2 P8 Matching variation after HCI stress in advanced CMOS technology for
analog applicationsJ. C. Lin1,3, S.Y.
Chen2, H.W. Chen2, H.C.
Lin2, Z.W. Jhou2, S.
Chou1, J. Ko1, T.F.
Lei3, H.S. Haung2 P9 One time programming device yield study based on anti-fuse gate oxide
breakdown on P-type and N-type substratesN. Mathur, Y. Ahn, I. Kouznetov, F. Jenne,
J. Fulford, Cypress Semiconductor Inc.
P10 Length scaling effects on dual damascene copper interconnects
electromigration M.H. Lin, K.P. Chang, K.C. Su, UMC, T. Wang, National Chiao-Tung Univ.
P11 IREM usage in the detection of highly resistive failures on 65 nm products I.
Wan, D. Bockelman, Y. Xuan, S. Chen, Intel
P12 Predictive simulation to improve reliability of a snapback-based NMOS clamp
P. Gaitonde et al., Florida Institute of Technology
P13 An investigation on substrate current and hot carrier degradation at elevated
temperatures for nMOSFETs of 0.13 µm technologyJ. C. Lin et al., UMC
P14 Determination and characterization of EOS-induced on submicron devices using 2D
IR spectral imaging techniqueM.F. Bailon, P.F.F. Salinas, J.P.S. Arboleda,
J.J.C. Miranda, Intel Tech. Philippines
P15 First steps toward aging simulation of complex analog circuits with
behavioural modelingF. Marc, Y. Danto, Université Bordeaux
P16 Some applications of
Vbd and Qbd testsJ.T.C. Chen, T. Dimitrova, D.
Dimitrov, Four Dimensions, D.K. Schroder, Arizona State University
P17 Accurate method for determination of interconnect cross section X.
Federspiel, Philips Semiconductors, D. Ney, V. Girault, STMicroelectronics
P18 Resistance instability in Cu-damascene structures during the isothermal electromigration testM. Impronta1, S. Farris1, A. Ficola2, A. Scorzoni1,2 To be announced… For more details, please contact: IRW Poster Sessions Chair Dept. ESM 212 EES
Bldg ph: (814) 863-4630 fax: (814) 863-7967 IRW Poster Sessions Vice
Chair Dept. ESM 212 EES
Bldg ph: (814) 863-4630 fax: (814) 863-7967
1Université de ToursLMP;
2STMicroelectronics
1Technical University at Wien;
2Cypress Semiconductor; 3AMD Saxony
1JPL; 2University of Maryland
1United Microelectronics Corp.;
2National Taipei University of Technology;
3National Chiao Tung University
1Institute for Microelectronic and Microsystems (CNR-IMM)
2University of Perugia