Overview

Reliability has not been a product differentiator for quite some time; high quality and reliability are a necessary prerequisite for entry into a market. Nowhere is this more true than in the electronics industry, where customers have come to expect high performance and reliability with almost any purchase they make.

In the past, meeting these requirements has not been a serious challenge for the silicon content of products: intrinsic wearout mechanisms took place far enough out in time that there was ample reliability margin by design, extrinsic defects were adequately screened early enough in the process through defect-based test methods that very few latent problems were put into packages, and finally, burn-in was capable of providing sufficient acceleration to weed out the few remaining latent defects that might have made it into the final application.

With the advent of 90nm production processes, moving rapidly to 65nm and beyond, the introduction of a variety of new materials, and the continuing quest for performance, intrinsic reliability margins have all but disappeared, test methods are struggling to capture defects that hide in the background timing and current drain, and voltage and temperature stress conditions are severely constrained in their ability to accelerate failure mechanisms.

The discussion will include (but not be limited to) product reliability assessment; defect detection and screening methods; burn-in and it's reduction, elimination, and ownership; use condition measurement and lifetime determination; and alternative reliability screening techniques.

Below are a list of questions I would like to use to stimulate discussion. Please give them some thought, and provide your expertise in these areas, or feel free to supplement them with additional material.

NOTE: If you plan on attending, please download the questionnaire, complete it, and return to ynelson@qualcomm.com by 10/10/05. Thank you for helping to improve the efficiency of the IRW discussion groups.

Questionnaire (as a WORD document) (as html)

Questions

1. How is product reliability determined?

a. Accelerated tests.

b. Field tests.

c. Modeling.

2. What drives lifetime requirements and who determines their adequacy?

a. Customer feedback.

b. Expected product replacement timeframe.

c. Field return data.

d. Process and/or product capability.

3. How are use conditions determined?

a. Instrumented products in the field.

b. Customer surveys.

c. Focus groups.

d. Manufacturer expectations.

4. How are new materials and processes driving burn-in conditions?

a. Shorter times.

b. Lower temperatures.

c. Reduced voltages.

d. Burn-in removal for some applications.

5. What other screening techniques or information are being used to supplement, reduce, or eliminate burn-in?

a. Bin-level statistical analysis (e.g. good die in bad neighborhoods).

b. Advanced IDDq (e.g. delta-IDDq, IDDt, etc.).

c. Parametric outlier detection.

d. Wafer-level burn-in.

e. Wafer Level Reliability.

f. Product maturity.

6. What are the risks and mitigation strategies being employed to reduce or remove burn-in?

a. Targeted applications.

b. Field return monitoring and early reaction.

c. Accelerated testing.

d. HALT/HASS.

e. Rogue/maverick lot detection and containment.

f. Design redundancy and robustness.

7. What are the differences between Foundry, captive fab, and customer expectations for burn-in and other screening techniques?

a. Die sales versus package parts.

b. Known-good die contracts.

c. Ownership of the screening process versus yield and process knowledge.

8. How do low-volume, high-reliability markets deal with commercial reality?

a. High per-part costs for customer screening.

b. Lack of visibility into manufacturing processes.

c. Little ability to influence part suppliers.

d. Outsourcing of reliability screening and testing.

9. How are new defect mechanisms, materials, and designs affecting defect coverage metrics?

a. High-k gate dielectrics.

b. Low-k interlayer dielectrics.

c. Reduced thickness liner materials.

d. Strained gate structures.

e. Reduced pitch wiring.

f. Resistive vias.