Tutorials:  

-          1) ESR             Pat Lenahan                        (2 hr)

-          2) SRAM          Bruce Woolery                     (2 hr)

-          3) Flash            Neal Mielke                         (2 hr)

-          4) Hi K            G.Bersuker                           (2 hr)

-          5) F/A              E. Cole                                 (2 hr)

-          6) Radiation     Allan Johnston                   (2 hr)

 

1. ESR - tools for characterization of degradation mechanisms in thin

gate dielectrics  (2 hr)

Detection of Atomic Scale Defects in MOS Reliability Problems

P.M. Lenahan

The Pennsylvania State University

University Park, PA 16802

 

This tutorial will have two goals. (1) This tutorial will introduce attendees to magnetic resonance techniques which have the power to identify the atomic-scale defects involved in MOS reliability problems. (2) This tutorial will provide a fairly detailed discussion of magnetic resonance results on reliability defects involved in several areas: negative bias temperature stressing of SiO2 and plasma-nitrided oxide pMOSFETs, interface/interlayer dielectric/bulk trapping centers in HfO2-based MOS devices, hot carrier induced defects, and stress induced leakage defects. An attempt will be made to integrate the two aspects of the presentation by illustrating particular resonance techniques with application to specific reliability issues. For example, the electrically detected magnetic resonance techniques of spin-dependent tunneling and spin-dependent recombination are very useful in studies of the negative bias temperature instability. These techniques will be explained, in part, in terms NBTI studies. Conventional electron spin resonance has been quite useful in studies of trapping defects in HfO2 and SILC in conventional oxides. HfO2 trapping and SILC will be utilized as specific examples in doing conventional electron spin resonance.

 

 

Patrick M. Lenahan

P.M. Lenahan earned his B.S. degree from the University of Notre Dame and his Ph.D. from the University of Illinois, Champaign-Urbana. After completing his Ph.D. in 1979, he was a post-doctoral fellow at Princeton University in 1979 and 1980.  From 1980 until 1985 he was a member of the technical staff in the Materials Research Directorate of Sandia National Laboratories in Albuquerque, New Mexico.  Since 1985 he has been at Penn State University where he is Distinguished Professor of Engineering Science and Mechanics (ESM).  ESM is the materials engineering and applied physics department of the Penn State Engineering College; the department also operates an honors degree program for engineering students interested in applied physics.  In 2001, he was visiting professor of Electronics and Computer Engineering at Nihon University, Tokyo, Japan (Nihon University is the largest university in Japan). From 2000-2005, he also served as associate editor of the Journal of Electronic Materials. He has authored over 150 publications, approximately 250 conference presentations, and one patent.  The publications have been cited approximately 3000 times in the technical and scientific literature.  His research has been primarily focused upon the trapping centers in HfO2, amorphous SiO2, nitrogen, phosphorous, and boron “doped” SiO2, silicon nitrides, silicon oxynitrides, Si/SiO2 interfaces, SiC/SiO2 interfaces, and silicon grain boundaries with a variety of electrical measurements and electron spin resonance techniques Current interests include NBTI, materials problems in high-k gate dielectrics, and material problems in SiC MOSFETs and BJTs.

 

 

 

 

 

 

2. SRAM reliability  (2 hr)

 

 

Current Issues in SRAM Reliability

Bruce Woolery, Intel

 

Abstract:

The drive for increased functionality and performance of integrated circuits drives greater integration, including the integration of larger embedded memories.  The technology enablers for larger memories include smaller dimensions, new materials, and new device structures, each with reliability risks.  In this tutorial, we will discuss the impacts of leakage and Vt shifts, device scaling impact, narrowing Vdd window, and the advantage of error correction.

 

Bio:

Bruce Woolery is a program manager for logic technology development quality and reliability at Intel.  He is responsible for reliability of next generation logic technologies.  He has held several technical and management positions in manufacturing, logic process development, and quality & reliability.  He has worked on the development and transfer into high volume manufacturing of the last 8 generations of technology.  Woolery received a bachelor's degree in chemical engineering from the University of California, Davis in 1977.

 

 

 

 

 

3. FLASH reliability - degradation and failure mechanisms in NAND/NOR NVM  (2 hr)

 

Reliability of Floating-Gate Flash Memories

Neal Mielke,  Intel

 

This tutorial reviews the basic operation of NOR and NAND floating-gate Flash memories and then describes their dominant reliability degradation mechanisms.  Media-management methods in component and system design for dealing with these mechanisms are covered.  Finally, product and technology qualification methods are discussed.

 

 

Bio:

Neal Mielke received his B.S. in physics and M.S.E.E. from Stanford University in 1979 and joined Intel that year.  He has focused on the development and reliability characterization of nonvolatile memory and logic technologies.  He has 20 patents and 19 publications, mostly related to nonvolatile memories.  He is currently Intel Fellow, Director of Reliability Methods.  He serves on the Board of Directors for IRPS, the Advisory Committee for TDMR, and the IEEE EDS Device Reliability Physics Committee, and he has been active in defining JEDEC reliability standards.

 

 

 

4. HiK reliability - trapping, leakage and breakdown  (2 hr)

 

Reliability assessment methodology for high-k gate stacks

Gennadi Bersuker

 

    High-k/metal gate stacks are entering the production stage that requires addressing practical characterization issues. It raises the question of how much we can rely on the extensive methodology/characterization experience accumulated for the conventional SiO2-type dielectrics taking into account that the SiO2 layer is usually a component of the multilayer high-k gate stack. The tutorial discusses general validity of the accelerated stress approach, and concentrates on delineating contribution to device instability from the high-k and oxide layers in order to assess stress-generated damage vs. activation of the process-related defects, which is critical for correct lifetime evaluation.

 

Bio:

Gennadi Bersuker completed his M.S. and Ph.D. in Physics at the Leningrad State University and Kishinev State University (USSR), respectively. After graduation, he joined Moldavian Academy of Sciences, and then worked at Leiden University (The Netherlands) and the University of Texas at Austin. Since 1994, he has been working at SEMATECH on process induced charging damage, electrical characterization of Cu/low K interconnect, advanced CMOS process development and high K gate stacks.

 

 

 

 

5. FA for identification of reliability issues (2 hr)

 
 

Beam-Based Defect Localization in ICs

Edward I. Cole Jr., Sandia National Laboratories, Albuquerque, NM

 

This tutorial will review standard and new electron and laser based tools for localizing defects, including so-called "soft" defects and what's being done in solid immersion lens technology for improving backside spatial resolution, with a few comments on the future.  Best practices and limitations will also be discussed.  All of these techniques can be performed on a standard SEM or SOM (using the proper laser wavelengths). The tutorial's goal is to provide beneficial information to both novice and experienced failure analysts. Topics are: 1) Standard techniques: secondary electron imaging for surface topology, voltage contrast, capacitive coupling voltage contrast, backscattered electron imaging, and electron beam induced current imaging; 2) Specialized SEM techniques: novel voltage contrast applications, resistive contrast imaging, and charge-induced voltage alteration (both high and low energy versions); and 3) SOM techniques: light-induced voltage alteration, thermally-induced voltage alteration/optical beam induced resistance change, Seebeck Effect imaging, soft defect localization, and light alteration defect analysis.

 

Ed Cole bio:

Edward Cole, Jr. received the B.S. (1981), M.S. (1985), and Ph.D. (1987) in physics from the University of North Carolina.  He joined the Failure Analysis Department of Sandia National Laboratories in 1987.  His research interests are in the development and improvement of non-destructive IC failure analysis tools, with emphasis on electron and optical beam techniques and he has published frequently in the field of failure analysis. Two failure analysis techniques developed by teams Dr. Cole led won R&D 100 awards in 1995 (CIVA) and 1998 (LIVA).  In 1995 Dr. Cole was named a Distinguished Member of the Technical Staff at Sandia National Laboratories and in 2005 a Sandia Senior Scientist.  He has served on the executive and management committees of the ISTFA and IRPS conferences, chairing the ISTFA’96 event and the IRPS’07 symposium.  He is a past president of the Electronic Device Failure Analysis Society (EDFAS) and currently the EDFA magazine editor.                    

 

 

 

 

6. Radiation effects – (2 hr)

 

Semiconductor Device Scaling:  General Trends and Reliability Implications for Space

Allan Johnston,  JPL

 

 

Abstract

     Advanced semiconductor devices continue to advance at an almost unprecedented rate, requiring extensive changes in the underlying device structure.  This paper will discuss general features of device scaling, discussing some of the tradeoffs that affect reliability.  Additional de-rating factors are usually required to use these devices in space, as well as system-level designs that incorporate fault tolerance.  Space radiation imposes additional difficulties, including catastrophic latchup from energetic cosmic rays.  In some cases scaling helps radiation hardness, but it can also make radiation problems more severe.  The material will be based on recent advances in the reliability and radiation effects literature, as well as on specific experience at JPL in qualifying and fielding space systems.  A brief discussion of radiation hardened methods will also be included.

Several topics will be included, including

·                   Reliability and scaling issues for rad-hard devices

·                   Reliability of SOI vs. bulk rad-hard, and

·                   Rad-hard circuit design

·                    

Biography

Allan Johnston is a Principal Engineer at the Jet Propulsion Laboratory, where he directs applied research on radiation effects in electronic and optoelectronic devices for NASA space applications.  He has been at JPL for fourteen years.  Previous experience included more than twenty years at the Boeing Aerospace Company on radiation effects and reliability in microelectronics and aerospace systems, where he managed a research group on reliability, radiation effects, and fault-tolerant computing.  He holds B.S. and M.S. degrees in physics from the University of Washington, Seattle, Washington. 

His technical interests include ionization and single-event upset effects in semiconductor devices, with particular emphasis on low dose-rate effects, latchup, and applications of advanced technologies in space.  Related interests include determining how new device technologies and device scaling will influence their radiation performance and reliability in space as well as radiation effects on optoelectronic devices.  He has been the author or coauthor of more than 90 papers in refereed journals.  He received the Outstanding Paper award at the IEEE Nuclear and Space Radiation Effects Conference (NSREC) in 1999, Meritorious Paper Awards in 1994, 1995 and 1996, and the Distinguished Poster Paper award in 1987.   Key publications include work on super-recovery (rebound) in MOS devices, latchup from single particles, dose rate effects in linear integrated circuits, the effects of device scaling on radiation susceptibility, and radiation effects in LEDs, optocouplers and laser diodes.  He published invited papers on latchup in the IEEE Transactions on Nuclear Science (TNS) in 1996, on device scaling at the RADECS-1997 and RADECS-2002 Conferences, on optoelectronics in the TNS in 2003, and a tutorial session on SEE effects in the 2002 IRPS.  He will give a plenary talk at the 2007 EOS/ESD Conference.    

He has been active in the IEEE Nuclear and Radiation Effects Conference, serving as Short Course Instructor for five conferences, Local Arrangements Chairman, Short Course Chairman, and Awards Chairman.  He was Technical Program Chairman for the 1997 NSREC, and General Chairman for NSREC in 2003.  He is a Fellow of the IEEE.