Hafnium-based dielectrics are being widely investigated as potential candidates for the gate dielectric in advanced gate stacks. Significant progress has been made in fabricating high-k gate stack transistors meeting ITRS requirements for low equivalent oxide thickness (1.0 nm), low leakage current (1-10 A/cm²) and high mobility (90% of SiO₂). However, specific features of high-k gate stacks, in particular, its multi-layer structure and high density of as-grown structural defects in the transition metal oxides complicates the evaluation of their intrinsic electrical characteristics and reliability. Pre-existing defects, some representing electron traps, give rise to the fast transient charging (FTC) phenomenon, which is shown to cause threshold voltage instability and mobility degradation. The presence of the SiO₂ layer at the interface between the hafnium-based dielectric and the substrate, the properties of which can be affected by the specifics of the gate stack fabrication process, makes it more difficult to identify the location and origin of the stress-generated fixed charges and electron/hole traps. Therefore, correct theoretical assessments of the advanced gate stack properties are required while also calling for novel measurement techniques, as well as thorough analysis and careful data interpretation of conventional electrical characterization techniques. The discussion will be a two-part series where Session I will focus on characterization and Session II will focus on the nature of these bi-layer stacks from a theoretical point of view.