IRW 2007 · October 15-18, 2007
Stanford Sierra Conference Center, Fallen Leaf Lake, California

The Integrated Reliability Workshop focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and future semiconductor applications as well as for ample opportunities for discussions and interactions with colleagues.

Hot reliability topics for the workshop include: high-k and nitrided SiO₂ gate dielectrics, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, product reliability and burn-in strategy, impact of transistor degradation on circuit reliability, reliability modeling and simulation, SiGe and strained Si, III-V, SOI, optoelectronics, single event upsets, and reliability assessment of novel devices, organic electronics, emerging memory technologies, and future “nano”-technologies.