Refereed  Posters

 

 

P1.  OTCP for radiation effect analysis in short and narrow LDD-channel transistor with LOCOS field oxide isolation—H. Tahi, B. Djezzar, and B. Nadji, CDTA

We have presented a methodical approach to take out the LOCOS (Local Oxidation of Silicon) and LDD (Lightly Doped Drain) sub-diffusion effects from charge-pumping (CP) curves, respectively, leaving only the CP-current of the effective channel, in narrow and short channel MOSFET transistors. Firstly, we have clarified the contribution of LDD sub-diffusion and LOCOS regions to the CP characteristics by studying the spatial distributions of CP threshold and flat band voltages. We have shown that the maximum Cpcurrent is the contribution of pumped current in effective channel, LOCOS and LDD sub-diffusion regions. Secondly, we have successfully used the Oxide-Trap Charge-Pumping (OTCP) to extract the radiation-induced oxide-trap (ΔN_ot) and interface-trap (ΔN_it) in effective short and narrow channel transistors. Finally, we have performed a comparison between OTCP and Capacitance-Voltage (CV) method.

P2.  In Situ measurement of reactive ion etching using an integrated MEMS sensor and a low-power charge-based capacitive sensing interface circuit—B.G. Morris and G.S. May, Georgia Institute of Technology

This paper describes a novel technique for monitoring film thickness in the reactive ion etching (RIE) process that incorporates a micromachined sensor. The RIE sensor relies on capacitive transduction to detect small capacitance changes and the resulting change in resonant frequency during the RIE process.  As an application vehicle, process control was demonstrated in the PlasmaTherm SLR series RIE system located in the Georgia Tech Microelectronics  Research Center.

P3. The effect of Cu contamination on device reliability in DRAM—J.W. Pyun, M.S. Jung, H.W. Kim, N.H. Cha, S.J. Hwang, J.S. Kang, and B.S. So, Samsung Electronics Co., Ltd.

The Cu out-diffusion from the direct contact (DC) bottom to the adjacent gate was observed for the failed samples with high temperature storage (HTS) stressing. HTS tests were performed at various temperatures to extract the activation energy for HTS failure. The predicted lifetime for the samples with Cu contamination was found to be 12 years at normal operating condition without stressing bias. Even though the root cause of the Cu contamination was not clearly revealed, based on the diffusion distance of Cu in silicon (Si), we speculated that the Cu contamination can be caused by the Cu migration into Si from the backside of wafer when the contamination was involved with one of packaging processes.

P4.  The hot carrier and NBTI reliability of a novel STI-based high-voltage PMOS device (>40V)—Q. Fu and C. Xu, Saarland University

P5.  Gate oxide integrity by initial gate current—S. Park, S. Hwang, J. Kang, B. So, and D. Baek, Samsung Electronics

A new and accurate approach to gate oxide reliability measurements for the determination of the gate oxide quality and lifetime estimation on MOSFET is presented. An accurate gate oxide thickness calculation by gate current provides oxide thickness variations better than conventional CV measurement.  A gate oxide quality by gate current analysis is well correlated to the time dependent dielectric breakdown (TDDB) method. The results present that oxide lifetime is better at lower gate current in same oxide thickness where device process is same but different fabrication facilities (FAB).

P6. Methodology for 3-dimensional high-density capacitor reliability evaluation—G. Fiannaca, P. Gardes, L. Berneux, E. Bouyssou, and C. Anceau, STMicroelectronics

Wafer level accelerated testing is a key tool to perform fast reliability assessment of new technologies. This paper presents an innovative methodology developed to perform accurate life-time extrapolation of 3-dimensional (3D) high density capacitors through Constant Electric field Stress (CES) test. This methodology is first based on dielectric thickness extraction from planar capacitors measurements. CES tests are then performed on 3D capacitors, adjusting the voltage stress with respect to the local dielectric thickness previously extracted. The efficiency of the methodology is demonstrated through Constant voltage Stress (CVS) and CES test results comparison.

P7.  Stress voltage dependence HCI induced traps distribution in 60V LDNMOS—S.K. Samanta, N. Patel, K.N. ManjulaRani, and K. Jang, Cypress Semiconductor

Lateral drain extended NMOS (LDNMOS) are widely used for integrated smart power application as it is compatible with standard CMOS flow and capable of handling of 20-160V [1]. However, when transistors are continuously stressed under high voltage drain and gate operation, most important and challenging concern is the proper perception of hot carrier degradation mechanism along with the location of trap distribution for minimizing Ron (on-state resistance, the most important figure-of-merit while switching several Amps of current) degradation and projecting the safe operating area (SOA). In this paper, lateral interface trap (Nit) distribution using charge pumping technique (CP) [2] is determined to present the mechanism of HCI degradation. It is also verified and correlated using TCAD simulation of impact ionization.

P8.  Hot-carrier reliability study and simulation methodology development for 65nm technology—K.N. ManjulaRani, R.M. Mooraka, N. Patel, S. Samanta, G. Narasimhan, N. Lakshminarayanan, R. Kapre, and H. Puchner, Cypress Semiconductor

P9.  The use of Taguchi method for process design of experiment to resolve gate oxide integrity issue—T. Cahyadi, P.Y. Tan, M.T. Ng, T. Yeo, J.J. Boh, and B. Fun, Chartered Semiconductor Mfg Ltd.

This paper discusses the process improvements for resolving gate oxide integrity (GOI) issue using the Taguchi method through reliability engineering for eliminating shallow trench isolation (STI) edge failure mode. The selected process parameters are narrowed down to STI/ILD stress, silicide residue, nitride residue, and other surface contaminants. The analysis of S/N ratio that the most GOI improvement comes from skipped N2 sacrificial oxide annealing.

P10. Effects of various applications on relative lifetime of processor cores—T. Gupta, O. Heron, T. Zimmer, N. Ventroux, F. Marc, and C. Bertolini, CEA LIST

P11. The Helium Ion Microscope for interconnect material imaging—W. Thompson, Carl Zeiss SMT, S. Ogawa, Semiconductor Leading Edge Technologies, Inc., L. Stern, L. Scipioni, and J. Notte, Carl Zeiss SMT

The recently developed helium ion microscope (HIM) can be operated in three imaging modes; ion induced secondary electron (SE) mode, Rutherford Backscatter imaging (RBI) mode, and scanning transmission ion imaging (STIM) mode. When low k dielectric or copper interconnects are imaged in these modes, it was found that unique pattern dimension and fidelity information at sub-nanometer resolution is available for the first time. Our talk will discuss the helium ion microscope architecture and the imaging modes that may make it a tool of particular value to the low-k dielectric and dual damascene copper interconnect technology.

P12. Improvement on erase characteristics of SONOS flash memory by Bandgap Engineering of tunnel oxide—D.H. Li and B.-G. Park, Seoul National University

P13. fWLR supported process development based on V- and J-ramp stress tests—A. Aal, ELMOS Semiconductor AG

Modern semiconductor manufacturing facilities employ stringent fWLR monitoring concepts to their lines to fulfill today’s quality and product reliability requirements. However, today’s fWLR is already far more than only addressed to monitoring. It is a concept that drives reliability growth. In this paper voltage and current based ramp concepts are reviewed and it will be explained how their use can be extended to technology/process design and development.

P14. Fast and simple method for estimation and separation of radiation-induced traps in MOSFET devices—B. Nadji, H. Tahi, and B. Djezzar, CDTA

In this work, we have proposed a simple and fast method to estimate the radiation-induced traps in P and N-MOS transistors independently. This method is based on standard SubThreShold Slope and Charge Pumping (I (V)-CP) to separate the radiationinduced border-traps and true interface traps, were the radiation-induced oxide traps are extracted classically by measuring the threshold voltage or Mid-Gap voltage shift. The CP curves are measured using respectively, the rise and fall saw signal for N-and PMOS to minimize the border trap estimation error caused by a difference in the band gap scan of I-V and CP. Emphasis is made on critical comparison between the radiation induced border traps extracted using I(V)-CP and classical method such as OTCP and DTBT. According to experimental data, the I(V)-CP method is more accurate than OTCP and DTBT methods, since it’s more sensitive than OTCP method for the extraction of border traps and it can gives all kinds of traps for P and N-MOS transistors separately.

P15. Correlation of electrical properties with interface structures of CVD oxide-based oxynitride tunnel dielectrics—Z. Liu,  H. Ishigaki, S. Ito, T. Ide, M. Makabe, NEC Electronics Corp.

We compare the electrical properties and interface characteristics in terms of nitrogen depth distribution and hydrogen diffusion behavior of two CVD oxide tunnel films that were nitrided by NO and N2O gas, respectively. The N2O-oxynitride shows a stronger resistance against the approach of the SiO2/Si interface by diffusing hydrogen in nuclear reaction analysis. This H diffusion behavior correlates with a characteristic N distribution in the tunnel oxide. The superior electrical quality of N2O-oxynitride over the NO-oxynitride is attributed to the existence of a N-rich H-diffusion barrier layer in the front of the oxynitride/Si interface.

P16.  IMD stack thermal resistance effects on SiCr thin film resistor’s current density performance—F. Downey, Analog Devices

P17. The investigation of the electro-thermal characteristics of a GTO thyristor at turn off using Silvaco Atlas—J. Ciezki, U.S. Naval Academy, G. Vineyard, T. Weatherford, Naval Postgraduate School

P18. Effects of statistical thin-oxide thickness variations on the time-dependent dielectric breakdown (TDDB) parameters for wafer level reliability—A.A. Keshavarz and L.F. Dion, STM

P19. TCAD analysis of self heating in AlGaN/GaN HEMTs under pulsed conditions—T. Weatherford, Y. Wang, and S. Tracey, Naval Postgraduate School

P20. An improved fast Id-Vg measurement technology with expanded application range—C. Wang^1,2,3, L.C. Yu^1,4,  J.P. Campbell¹, K.P. Cheung¹, Y. Xuan², P.D. Ye², J.S. Suehle¹, D.W. Zhang⁴

                                          ¹NIST;   ²Purdue Univ.;   ³Fudan Univ.;    ⁴Rutgers Univ.

P21. Negative bias temperature instability performance enhancement with process integration of high current fluorine incorporation in source/drain extension and O2 gas ashing in post poly resist strip and sSpacer etch asher process in 45nm CMOS Technology—S. Mahesh, X. Bin, S. Yongliang, Karim, L.Yu, Z. Xu, O. Hung, and C. Weihua, Chartered Semiconductor Mfg. Ltd.

P22. Effect of metal thickness variations on metal lifetime due to electromigration— A.A. Keshavarz and L.F. Dion, STMicroelectronics

In common agreement with Negative Bias Temperature instability (NBTI) as a serious Front-end reliability issue, great efforts were made in recent years to investigate NBTI mechanism, characterization techniques and performance improvement. In this work authors focused on device NBTI performance improvement from combined impact of multiple process steps integration relating to SiON/Si interface quality. The effect of process integration of High Current Fluorine incorporation in Source/Drain extension along with O2 gas Asher process for post poly resist strip (PRS) and spacer etch process (SPE) on NBTI performance for thin gate regular Vt transistor and SRAM were investigated. Through our work, we demonstrated that by correctly chosen thermal budget and nitrogen profile, the high current fluorine implantation in S/D extension and O2 gas asher process decrease interface state component of NBTI to greater extent and thus facilitate to achieve enhanced NBTI performance to meet end-of-lifetime specifications.