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IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP
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October 18-22, 2009 |
Refereed & Open Poster Sessions(Monday, and Wednesday Evenings)Chair: David Roy, STMicroelectronics; david.roy@st.comVice-Chair: Jin Qin, University of Maryland; qjin@umd.edu |
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In addition to our refereed poster sessions featured below, all attendees have the opportunity to present a poster to communicate and discuss their ideas and newest results on technical projects or issues. Please indicate in the space provided on the registration form your intention to bring a poster. A poster display board (32" x 40" or 81 cm x 100 cm) will be reserved for you. Your work should be in landscape format on 8½ x 11" or A4 paper with a maximum of twelve pages. This is a great opportunity for you to share your work with your peers. Also feel free to bring last minute results, board space will be found for you. P1. OTCP for radiation effect analysis in short and narrow LDD-channel transistor with LOCOS field oxide isolation—H. Tahi, B. Djezzar, and B. Nadji, CDTA P2. In Situ measurement of reactive ion etching using an integrated MEMS sensor and a low-power charge-based capacitive sensing interface circuit—B.G. Morris and G.S. May, Georgia Institute of Technology P3. The effect of Cu contamination on device reliability in DRAM—J.W. Pyun, M.S. Jung, H.W. Kim, N.H. Cha, S.J. Hwang, J.S. Kang, and B.S. So, Samsung Electronics Co., Ltd. P4. The hot carrier and NBTI reliability of a novel STI-based high-voltage PMOS device (>40V)—Q. Fu and C. Xu, Saarland University P5. Gate oxide integrity by initial gate current—S. Park, S. Hwang, J. Kang, B. So, and D. Baek, Samsung Electronics P6. Methodology for 3-dimensional high-density capacitor reliability evaluation—G. Fiannaca, P. Gardes, L. Berneux, E. Bouyssou, and C. Anceau, STMicroelectronics P7. Stress voltage dependence HCI induced traps distribution in 60V LDNMOS—S.K. Samanta, N. Patel, K.N. ManjulaRani, and K. Jang, Cypress Semiconductor P8. Hot-carrier reliability study and simulation methodology development for 65nm technology—K.N. ManjulaRani, R.M. Mooraka, N. Patel, S. Samanta, G. Narasimhan, N. Lakshminarayanan, R. Kapre, and H. Puchner, Cypress Semiconductor P9. The use of Taguchi method for process design of experiment to resolve gate oxide integrity issue—T. Cahyadi, P.Y. Tan, M.T. Ng, T. Yeo, J.J. Boh, and B. Fun, Chartered Semiconductor Mfg Ltd. P10. Effects of various applications on relative lifetime of processor cores—T. Gupta, O. Heron, T. Zimmer, N. Ventroux, F. Marc, and C. Bertolini, CEA LIST P11. The Helium Ion Microscope for interconnect material imaging—W. Thompson, Carl Zeiss SMT, S. Ogawa, Semiconductor Leading Edge Technologies, Inc., L. Stern, L. Scipioni, and J. Notte, Carl Zeiss SMT P12. Improvement on erase characteristics of SONOS flash memory by Bandgap Engineering of tunnel oxide—D.H. Li and B.-G. Park, Seoul National University P13. fWLR supported process development based on V- and J ramp stress tests—A. Aal, ELMOS Semiconductor AG P14. Fast and simple method for estimation and separation of radiation-induced traps in MOSFETs devices—B. Nadji, H. Tahi, and B. Djezzar, CDTA P15. Correlation of electrical properties with interface structures of CVD oxide-based oxynitride tunnel dielectrics—Z. Liu, H. Ishigaki, S. Ito, T. Ide, M. Makabe, NEC Electronics Corp. P16. IMD stack thermal resistance effects on SiCr thin film resistor’s current density performance—F. Downey, Analog Devices P17. The investigation of the electro-thermal characteristics of a GTO thyristor at turn off using Silvaco Atlas—J. Ciezki, U.S. Naval Academy, G. Vineyard, T. Weatherford, Naval Postgraduate School P18. Effects of statistical thin-oxide thickness variations on the time-dependent dielectric breakdown (TDDB) parameters for wafer level reliability—A.A. Keshavarz and L.F. Dion, STM P19. TCAD analysis of self heating in AlGaN/GaN HEMTs under pulsed conditions—T. Weatherford, Y. Wang, and S. Tracey, Naval Postgraduate School, P20. An improved fast Id-Vg measurement technology with expanded application range—C. Wang1,2,3, L.C. Yu1,4, J.P. Campbell1, K.P. Cheung1, Y. Xuan2, P.D. Ye2, J.S. Suehle1, D.W. Zhang4 1NIST; 2Purdue Univ.; 3Fudan Univ.; 4Rutgers Univ. P21. Negative bias temperature instability performance enhancement with process integration of high current fluorine incorporation in source/drain extension and O2 gas ashing in post poly resist strip and sSpacer etch asher process in 45nm CMOS Technology—S. Mahesh, X. Bin, S. Yongliang, Karim, L.Yu, Z. Xu, O. Hung, and C. Weihua, Chartered Semiconductor Mfg. Ltd. P22. Effect of metal thickness variations on metal lifetime due to electromigration— A.A. Keshavarz and L.F. Dion, STMicroelectronics
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