2009 IEEE INTERNATIONAL
Integrated Reliability Workshop
PROGRAM (preliminary)

SUNDAY, October 18   Please have lunch before arriving at the camp; no lunch will be served at the camp.

      3:00–6:00 p.m.       Registration: Pick up badges & handout (Lodge Lounge)

     Discussion Group and SIG Signup; Poster preparation

      3:00–8:00 p.m.       Lodge check-in. Get room assignment (prearranged) & room key.

     (If physically challenged please notify desk of special needs.)

      6:15–7:30 p.m.       DINNER, (Dining Room) authors: dine with your session chair

      7:30–9:00 p.m.       Tutorial #1: DNA Self-Assembled Nanostructures for Device Applications—Bill Knowlton, Boise State University

MONDAY, October 19

       7:00–8:00 a.m.       Breakfast (Dining Room)

       8:00–8:10 a.m.       (Angora Room) Welcome & Introduction: Guoqiao Tao, General Chair; Chad Young, Technical Program Chair

       8:10–9:00 a.m.       Keynote: Reliability in the More than Moore landscape—Dr. John Schmitz, VP Process Technology Research,
      NXP Semiconductors

     9:00–11:10 a.m.       Tutorial #2: International fWLR Monitoring Guideline—Andreas Martin, Infineon, Andreas Aal, ELMOS Semiconductor

   10:00–10:20 a.m.       Break

   11:10–12:00 p.m.       Session #1: Reliability, Chair: Rolf Geilenkeuser, GLOBALFOUNDRIES

1.1       Investigation of SILC via energy resolved spin dependent tunneling spectroscopys—J.T. Ryan, P.M. Lenahan, Penn State         University, A.T. Krishnan, S. Krishnan, Texas Instruments

1.2       New failure mechanism during high temperature storage testing and its application on SIV risk evaluation—O. Aubel, W. Yao, M.A. Meyer, H.J. Engelmann, J. Poppe, F. Feustel, C. Witt, GLOBALFOUNDRIES

     12:00–1:00 p.m.       Lunch, Dining Room

      1:15–2:45 p.m.       Tutorial #3: ESD Protection Design and Qualification Challenges—Charvaka Duvvury, Texas Instruments

      2:45–4:45 p.m.       Session #2:  Memory, Chair: William Tonti, IEEE

2.1       (Invited) Resistive switching characteristics of metal/perovskite oxide device for nonvolatile memory applications— H. Hwang, 

      3:15–3:40 p.m.       Break

2.2       Electric field dependent switching and degradation of resistance random access memory—K. Hosotani*, S.-G. Park, Y. Nishi, Stanford University        *on-leave from Tosiba Corporation

2.3       Threshold voltage (Vt) instability in high bit-count-per-cell floating-gate non-volatile memories—Guoqiao Tao, NXP

LN-1   A fast WLR test for the evaluation of EEPROM endurance—A. Uhlemann, A. Aal*, H. Vogt, Fraunhofer IMS    *ELMOS

      4:45–5:55 p.m.       Tutorial #4: NBTI: Why Won’t This Thing Go Away?— Jason P. Campbell, NIST    

      6:00–7:30 p.m.       DINNER, (Dining Room) authors: dine with your session chair

     7:30–10:30 p.m.       Announcements, Poster Session, & Mixer (Cathedral Room), Chair: David Roy, STM, Vice Chair: Jin Qin, U Maryland

TUESDAY, October 20

       7:00–8:00 a.m.       Breakfast (Dining Room)

       8:00–8:15 a.m.       Announcements (Angora Room)

       8:15–9:55 a.m.       Session #3: NBTI-1, Chair: Bill Knowlton, Boise State University

3.1       (Invited) Reassessing NBTI mechanisms by ultrafast charge pumping measurement—D.S. Ang, Z.Q. Teo, Nanyang Technology,  C.M. Ng, Chartered Semiconductor Manufacturing Ltd.

3.2       A study of NBTI by the statistical analysis of the properties of individual defects sites in pMOSFETS— H. Reisinger, T. Grasser*, C. Schlünder, Infineon Technologies                   *TU Wien

3.3       On the thermal activation of negative bias temperature instability reliability—R.G. Southwick III, W.B. Knowlton, Boise State University, B. Kaczer, IMEC, T. Grasser, TU Wien

3.4       What triggers NBTI? An “On The Fly” electron spin resonance approach—J.T. Ryan, P.M. Lenahan, Penn State University, T. Grasser, TU Wien, H. Enichlmair, austriamicrosystems AG

     9:55–10:10 a.m.       Break

   10:10–11:40 a.m.       Session #4: Future Technology–1, Chair: Chadwin Young, SEMATECH

4.1       (Invited) Organic electronic devices:  Evolution of performance and reliability—A. Dodabalapur, University of Texas–Austin

4.2       (Invited) Impact of surface preparation on the characteristics of InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs)—E.M. Vogel, University of Texas–Dallas

4.3       (Invited) Instabilities in oxide semiconductor transparent thin film transistors—J.F. Conley, Jr. Oregon State University

   11:40–12:00 p.m.       Group Picture                           

     12:00–1:00 p.m.       Lunch, Dining Room

      1:05–2:45 p.m.       Tutorial #5: BEOL Reliability Challenges and its Interaction with Process Integration—Oliver Aubel, GLOBALFOUNDRIES

      2:45–4:25 p.m.       Session #5: Back-end Reliability, Chair: Andreas Martin, Infineon

5.1       (Invited) Impact damage model for TDDB failure in low-k interlevel dielectrics—J.R. Lloyd, SUNY Albany

      3:15–3:35 p.m.       Break

5.2       Cu interconnect immortality criterion based on electromigration void growth saturation—P. Lamontagne1, L. Doyen1, E. Petitprez1, D. Ney1, L. Arnaud1,2, P. Waltz1, Y. Wouters3     1STMicroelectronics;  2CEA;    3SIMaP

5.3       Comprehensive characterization of BEOL-TDDB performance using very fast voltage ramp dielectric breakdown tests—O. Aubel, F. Feustel, T. Hoffmann, M. Majer, K.Yiang, GLOBALFOUNDRIES

      4:25–6:00 p.m.       Tutorial #6: Three Dimensional Systems Integration - Concepts and Challenges—Alan Mathewson, Tyndall Institute

      6:00–7:30 p.m.       DINNER, (Dining Room)       

    7:30–9:00 p.m.       Tutorial #7:  Reliability of gate dielectrics in MOSFETs: A nanometer scale approach with conductive atomic force microscopy—Montserrat Nafría, Marc Porti, Universitat Autònoma de Barcelona

     9:00–10:00 p.m.       Discussion Groups: Chair: Andrew Turner, IBM

            (One hour parallel sessions for each topic)  Attendees are to participate in one of the groups

                           

WEDNESDAY, October 21

       7:00–8:00 a.m.       Breakfast (Dinning Room)

       8:00–8:10 a.m.       Announcements, (Angora Room)

    8:10–9:10 a.m.       Tutorial #8: Degradation and Reliability of Metal Gate / High-k CMOS Technologies—Andreas Kerber, GLOBALFOUNDRIES

     9:10–12:00 p.m.       Session #6:  Transistor, Chair: Tibor Grasser, TU Wien

6.1       Application of fast wafer-level reliability PBTI tests for screening of high-k / metal gate process splits—G. Krause, R. Geilenkeuser, M. Trentzsch, F. Graetsch, L. Herrmann, GLOBALFOUNDRIES

6.2       Impact of instrumental current scatter on fast Bias Temperature Instability testing—A. Kerber, GLOBALFOUNDRIES, K. Zhao, B.P. Linder, and E. Cartier, IBM

   10:00–10:20 a.m.       Break

6.3       A fast, simple wafer-level Hall-mobility measurement technique—L.C. Yu1, 2), K.P. Cheung1), V. Tilak3), G. Dunne3), K. Matocha3), J.P. Campbell1), J.S. Suehle1), K. Sheng2)      1)NIST;    2)Rutgers University;   3)GE Global Research

6.4       Comprehensive analysis of the degradation of a lateral DMOS due to hot carrier stress—E. Riedlberger, C. Jungemann*, A. Spitzer, M. Stecher, W. Gustin, Infineon Technologies  *Bundeswehr University

6.5       Simulation of statistical aspects of reliability in nano CMOS—M.F. Bukhori, S. Roy, A. Asenov, University of Glasgow

6.6       Bias stability of zinc-tin-oxide thin film transistors with Al2O3 gate dielectrics—J. Triska, J.F. Conley, Jr., R. Presley, R. Schaffer, J.F. Wager, Oregon State University

     12:00–1:30 p.m.       LUNCH (Dining Room — Take out Lunch bags available)

      1:30–6:00 p.m.       Open         The afternoon is free for discussion, hiking & other recreation. All attendees are required to be back before darkness.

      6:00–7:30 p.m.       DINNER, Dining Room

      7:30–8:30 p.m.       Announcements, Poster Session, & Mixer (Cathedral Room), Chair: David Roy, STM, Vice Chair: Jin Qin, U Maryland

      8:30–9:30 p.m.       Discussion Groups: Chair: Andrew Turner, IBM

            (One hour parallel sessions for each topic)  Attendees are to participate in one of the groups

     9:30–10:30 p.m.       Individual SIG Meetings (to be announced at camp)

THURSDAY, October 22

       7:00–8:00 a.m.       Breakfast (Dining Room)

       8:00–8:50 a.m.       Session #7:  NBTI-2, Chair: Jason Campbell, NIST

7.1       A radically different model for NBTI in nitrided oxide MOSFETs—P.M. Lenahan, Penn State University

7.2       Analytical solution of the switching trap model for negative bias temperature stress—B. Bindu et al., TU Wien          

     8:50–11:10 a.m.       Session #8: Future Technology-2, Chair: Guoqiao Tao, NXP

8.1       (Invited) Transport in carbon nanostructures—T. Yamada, Santa Clara University

8.2       (Invited) Micro relay reliability improvement for digital logic applications—V. Pott, University of California at Berkeley

     9:50–10:20 a.m.       Break (Time to check out!)

8.3       Self-optimizing defect generation for advanced CMOS substrates—A.E. Islam, M.A. Alam, Purdue University

LN-2   The critical role of the defect structural relaxation for interpretation of noise measurements in MOSFETs—D. Veksler, G. Bersuker, H. Park, C. Young, K. Y. Lim, W. Taylor, SEMATECH

   11:10–11:35 p.m.       Session #9: Back-end Reliability-2, Chair: James Lloyd, SUNY Albany

9.1       Capacitance variation under electrical stress of SiOCH low-k dielectrics for the advanced 45nm technology node and beyond—M.Vilmay, D. Roy, S.Blonkowski, STMicroelectronics, F. Volpi, J-M. Chaix, SIMAP

   11:35–12:00 p.m.       DG Summary / SIG Report / Wrap-up

     12:00–1:00 p.m.       LUNCH, (Dining Room) & then the Workshop Ends— Attendees must

Leave the Stanford Sierra Camp unless attending JC14.2

2:00 p.m. Thursday to noon Friday         JEDEC 14.2 Committee on Wafer Level and Technology Reliability