P1. Evaluation of X-Ray Irradiation Defect on 65nm Multi Level cell NOR Flash Technologies—P. Navuduri, W. Melton, S. Eilert, A. Oen, Micron Technology, Inc., C. Abraham, S.-J. Wen, Cisco Systems, Inc.

P2. A Novel Virtual Age Reliability Model for Time-to-Failure Prediction—Y. Wang, S.D. Cotofana, Delft University of Technology

P3. Downstream Electromigration Improvement in 45nm Technology—Y. Zhao, X. Zeng, W. Liu, F. Zhang, Y.K. Lim, A. Du, Globalfoundries

P4. Evaluation on the Reliable Operation of a Gate-Level Pipelined Self Synchronous System Against PVT and Aging—B. Devlin, University of Tokyo

P5. Memory Reliability Model for Accumulated and Clustered Soft Errors—S.Y. Lee, S. Baeg, Hanyang University, P. Reviriego, Universidad Antonio de Nebrija

P7. An empirical model describing the MLC retention of charge trap flash memories—T. Melde, TU Dresden, R. Hoffmann, Fraunhofer CNT, E. Yurchuk, TU Dresden, J. Paul, Fraunhofer CNT, T. Mikolajick, TU Dresden

P8. TDDB Chip Reliability in Copper Interconnects—M. Bashir, D.H. Kim, S.K. Lim, L. Milor, Georgia Institute of Technology

P9. Degradation of Sub-micron Gate AlGaN/GaN HEMTs due to Reverse Gate Bias—E.A. Douglas, C.-Y. Chang, T. Anderson*, J. Hite*, L. Lu, C.-F. Lo, B.-H. Chu, D.J. Cheney, B.P. Gila, F. Ren, G.D. Via^**, P. Whiting, R. Holzworth, K.S. Jones, S. Jang^***, S.J. Pearton, University of Florida

*U.S. Naval Research Lab; **U.S. Air Force Research Lab; ***Dankook University

P10. SRAM Cell Reliability Degradations due to Cell Crosstalk—J. Bae, S. Baeg, Hangyang University, S.-J. Wen, R. Wong, Cisco Systems, Inc.

P11. The Effect of Radon on Soft Error Rates for Wire Bonded Memories—R. Wong, P. Su, S.-J. Wen, Cisco Systems, Inc., B.D. McNally, S. Coleman, XIA LLC, M. Zhang, T.-J. Shen, L. Lee, GSI Technology

P12. Understanding The Influence of Antifuse Bitcell Dimensions on The Programming Time and Energy Using an Analytical Model—M. Deloge, B. Allard, P. Chandelier, J. Damiens, E. Le-Roux, M. Rafik, STMicroelectronics

P13. Insights about Reliability of Heterojunction Bipolar Transistor under DC stress—F. Cacho, S. Ighilahriz, M. Diop, D. Roy, V. Huard, STMicroelectronics

P14. New DRAM HCI Qualification Method Emphasizing on Repeated Memory Access—C.-F. Chia, S.-J. Wen, Cisco Systems, Inc., S.H. Baeg, Hanyang University

P15. Qualification of 32 Gb MLC NAND Flash for Space Application—J. Heidecker, M. White, Jet Propulsion Laboratory

P16. 3D Simulation of Charge Collection and SEU of 0.13m PD SOI SRAM—X. Zhang, S. Yue, J. Li, Beijing Microelectronics Technology Institute

P17. RAAPS: Reliability Aware ArchC based Processor Simulator—T. Gupta

P18. Design-In Reliability for Over Drive Applications in Advanced Technology—J.-G. Ahn, P.-C. Yeh, J. Sowards, N. Lo, J. Chang, Xilinx, Inc.

P19. Improved Electrical Failure Analysis Methodology and Accurate Resistance Measurementfor Real DRAM Chip Transistors by Nanoprober Technique—H. Park, Samsung

P20. Complexities of the Non-Volatile Memory Reliability Testing Caused by the Test Structures—A.A. Keshavarz, G.S. Spawn, N.D. Reyes, R. Mincitar, L.F. Dion, STMicroelectronics

OPEN (walk-in) POSTERS

W1. Micro and Nano Device Reliability Control by MOS Transistors Mechanical Stress Sensitivity Estimation and Flexible, Customer Oriented Product Engineering Flow—G. Janczk, T. Bieniek, P. Grabiec, J. Szynka, S. Kalicinski, P. Janus, Institute of Electron Technology, Warsaw, Poland

W2. Determine Sample Sizes to Distinguish the Difference Between Two Extrapolated Lifetimes in Reliability Tests—J.J. Ma, S.F. Yang, W.T. K. Chien, SMIC, Shanghai

W3. Design for Reliability - Robust High Current and High Temperature AlCu Metallizations—M. Ackermanm, V. Hein, X-FAB AG, Erfurt, Germany

Platform Presenters

Poster Presenters