IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP

 

 

held October 16-20, 2011

Technical Program

 

Detailed Program Schedule from handout

Invited Talks: 

—Recent trends in CMOS reliability: 
from individual traps to circuit simulations — Ben Kaczer

—Separating NBTI and PBTI effects on the
degradation of ring oscillator frequency — Barry Linder

—Technology Variability and
Product Design Implications — David Fried

—JEDEC — Tim Sullivan

 

 

Refer to 2010 IIRW

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Refereed & Open Poster Sessions

(Monday and Wednesday Evenings)

Chair: Tibor Grasser TU Wien;  grasser@iue.tuwien.ac.at

In addition to our refereed poster sessions, all attendees have the opportunity to present a poster to communicate and discuss their ideas and newest results on technical projects or issues. Please indicate in the space provided on the registration form your intention to bring a poster.  A poster display board (32" x 40" or 81 cm x 100 cm) will be reserved for you. Your work should be in landscape format on 8½ x 11" or A4 paper with a maximum of twelve pages. This is a great opportunity for you to share your work with your peers. Also feel free to bring last minute results, board space will be found for you.

Preliminary Poster List:

Refereed Posters:

 

RP1    On-chip circuit for massively parallel BTI characterization—M.B. da Silva^1,2, B. Kaczer¹, G. Van der Plas¹, G.I. Wirth^{2
              1}UFRGS    ²imec

RP2    Impact of STI stress on hot carrier degradation in 5V NMOSFET—H. Jiang, H.K. Yap, S.M. Pandey, J.S. Park, J. Lim, X. Zeng, GLOBALFOUNDRIES Singapore

RP3    A new degradation mechanism of gate oxide reliability due to “extrinsic” responses of QBD along rough “Bird’s-Beak” frontline—L. Sheng, J. Gerlach, E. Glines, ON Semiconductor

RP4    Generation of single- and double-charge electron traps in tunnel oxide of flash memory cells under Fowler–Nordheim stress —Y. Tkachev and A. Kotov, Silicon Storage Technology

RP5    The effect of fluorine implant on NBTI behaviour in BCD-processes—E. Olthof, M. Combrie,
L. van Marwijk, J. Claes, J. Dubois, NXP Semiconductor, J. Thillaigovindan, W. Ng, SSMC      

RP6    TCAD-based failure analysis and modeling of pit formation in GaN HEMTs —T. Seigenthaler,
M. Porter, T. Weatherford, Naval Postgraduate School

RP7    Electromigration and stressmigration assessment of nanoscale reactive-ion-etch Al interconnect—
M.-Y. Lee, R. Tu, A.S. Teng, A. Kuo, C.C. Shine, D. Yen, H.-J. Lee and C.-Y. Lu, Macronix International

RP8    On the investigation of failure mechanisms during repetitive ESD pulses —M. Diatta, D. Trémouilles,
V. Marchebout, E. Bouyssou, and M. Bafleur, STMicroelectronics

RP9    Exploratory procedure for early wafer reliability evaluation and sorting for mass-produced multitask InGaAsP devices—D.E. Verbitsky

RP10  A practical approach to modeling product performance degradation and assigning lifetime reliability guard band —V.N. Shah, Y.-L. Tan, S. Wong, and T. Rodes, Advanced Micro Devices Inc.

RP11  Impact of gate length and gate oxide thickness on the relationship of FN-stress induced degradation parameters—Y.H. Kang, C.W. Lee, H.U. Kim, Y.K. Ryu, H.S. Kim, and T.S. Jung, Samsung Electronics

Open posters:

OP1    Device reliability studies of compound semiconductor devices using low frequency noise defect spectroscopy—Hemant Rao, Weikai Xu, Gijs Bosman, University of Florida

OP2    Product dielectric reliability assessment —J.K. Jerry Lee^1,3, S.Y. Pai¹, K.P. Chang², N.-F. Hsu², A. Juan², K.C. Su² ,        ¹Xilinx Inc.  ²United Electronics Corp.    ³currently at Cisco Systems

OP3    Joule heating temperature prediction for inductor pattern—Laurent Siegert^1,2, G. Fiannaca¹, G. Gautier^{2                         1}STMicroelectronics        ²François Rabelais University  

OP4    Transient TCAD analysis of breakdown in a Carbon Nanofiber (CNF) under constant current conditions —J. Brunton, T. Weatherford, Naval Postgraduate School, T. Yamada, Santa Clara University

OP5    Observation of Negative Bias Temperature Instabilities on parasitic p-channel MOSFET occurring during High-Temperature Reverse-Bias Stressing of trench-gated n-channel MOSFETs—Jifa Hao, M. Rioux, Fairchild Semiconductor, O.O. Awadelkarim, Penn State

OP6    The exploration of charge collection and SEU induced by angular strikes in partially depleted SOI SRAM by 3D simulation —Xiaochen Zhang,   Suge Yue, Jiancheng Li, Beijing Microelectronic Technology Institute

OP7    Lifetime estimation of ceramic LED packages using accelerated lifetime tests—Byungjin Ma, Jemin Kim, Sungsun Choi, Korea Electronics Technology Institute

OP8    Radiation evaluation of SEE in ASIC fabricated in 0.18µm technology—Pan Dong, Long Fan, Suge Yue, Hongchao Zheng, Shougang Du, Beijing Microelectronic Technology Institute

OP9    Logic stabilization of open fault LSI by laser beam irradiation—
Masaru Sanada, Kochi University of Technology

 2011 IIRW index