Wafer level reliability tests, test approaches, and reliability test structures:

• fast stress tests and analysis methodologies,
• reduction in development time,
• in-line monitors,
• relation to circuit-element and package-level tests,
• use and interpretation of WLR data,
• success stories,
• fine tuning of WLR implementation,
• accounting for censoring,
• design, characterization, and data analysis
  for chip or package level circuit-like structures
  (including electrical and/or physical test/analysis).