IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP
held   October 16-20, 2011

Keynote Address:

Scaling to the Final Frontier:

Reliability challenges in sub 20 nm technologies
Text Box: 2011 Keynote

Tanya Nigam
PMTS Technology & Integration Engineering
GLOBALFOUNDRIES

As we continue scaling towards 14 nm and beyond, reliability is becoming an integral part of the complete technology offering. Building in reliability is critical to the success of future scaling. As we marched towards the sub 100 nm technologies material changes have been necessary to meet the power, performance and reliability requirements. In sub 45 nm regime SiOx based dielectrics have been replaced by HK MG leading to new degradation mechanisms such as PBTI and also changed the understanding of existing mechanisms such as TDDB. Similar challenges exist for backend and middle-of-line reliability where scaling presents challenges for RC delay as well as metal and dielectric reliability.  Process solutions for improved electromigration reliability like alloy seed enhancement and metal capping degrade the resistance of interconnect and impact the dielectric reliability. Double patterning approaches also bring with them additional impacts to dielectric spacing and metal reliability. As we move beyond 20 nm new architecture and materials such as FINFETs and  III-V channels will appear. It is critical to leverage our learning from past and develop understanding and solutions for the upcoming challenges.

Text Box: Tanya Nigam Tanya Nigam received her Bachelor’s degree in Physics (Hons.) from St. Stephens College, Delhi University. She obtained a M.Sc in Physics from IIT Kanpur and a M.Sc in Electrical Engineering from the Katholieke Universiteit Leuven in 1995. Between 1995 and 1999, she obtained Ph.D in the area of ultra-thin gate oxides at IMEC, Belgium, in 1999. From 1999 until 2001, Tanya was a Member of Technical Staff at Bell Labs. During this period she worked on novel device geometries to overcome sub-50nm device challenges. From 2001 until 2005, she was with Agere Systems, formerly the Microelectronics Division of Lucent Technology. At Agere, she worked on reliability issues for power LDMOS devices, and HCI/NBTI reliability concerns for CMOS. From October 2005 till 2007 Tanya worked as a Senior Staff at Cypress Semiconductor involved in the optimization of 65nm CMOS. Since Jan 2008 she is working at AMD as SMTS, correlating device level degradation to product level degradation. Since 2009 she has been working at GLOBALFOUNDRIES. She is currently a Principle Member of Technical staff working in the area of Front End of Line reliability for sub 45 nm technologies. She has co-authored 40 papers in Journals and Conferences.

 2011 IIRW index

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