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IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP
CALL FOR PAPERS |
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We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics:
Designing-in reliability (products, circuits, systems, processes) Resistive memory: degradation mechanisms Deep sub-micron transistor and circuit reliability Customer product reliability requirements / manufacturer reliability tasks Root cause defects, physical mechanisms, and simulations Wafer level reliability tests, test approaches, and reliability test structures:
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Abstract submission deadline July 20, 2012 Please prepare your two-page extended abstract (maximum two pages including figures) in either an MS Word document or pdf format. All submissions will be acknowledged by email within one week. If you do not receive acknowledgment of your submission, please contact the Technical Program Chair. Your Abstract should state clearly and concisely the results of your work and why they are significant. Representative data and figures that support your proposal are REQUIRED. Technical Program Chair: Jason Campbell, National Institute of Standards and Technology 100 Bureau Drive, MS 8120, Gaithersburg, MD 20899 Tel: 301-975-8308 Email: jason.campbell@nist.gov
For more information, contact the Technical Program Chair |
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Author Instructions
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*Platform/Oral (pdf) |
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IIRW 2012 will include a special resistive memory invited session. Resistive memory abstract submissions are also encouraged. Additional hot reliability topics for the workshop include: high-k and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III-V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-x dielectrics, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, and single event upsets. |
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