IEEE IRW´98

August 1998

Dear IRW´98 attendee,
I would like to ask you to fill out the questionnaires of both discussion groups which you will attend during IRW´98. The descriptions of the discussion groups are provided on a separate Web page. This year the following four discussion groups are organised for the workshop:

• Interconnect Reliability - with a focus on copper.
• Oxides - ultra thin oxides.
• Electrostatic Discharge - requirements, testing, protection development.
• C-V Measurements - and its implication on oxide, transistor and non-volatile memory cell reliability.

Thank you very much for your time and cooperation. I am looking forward to meeting you at the camp in October´98.
Andreas Martin
(IRW´98 Discussion Group Chair)

1. What are your primary reliability concerns for interconnects? (Please list the mechanisms, e.g., electromigration, stress migration, corrosion, fracture, extrusions.)
2. What failure criteria do you use for EM? For SM? (E.g., 20% resistance shift, 10 Ohms shift, other?) Is it normalized to a specific structure?
3. Do you extract activation energy and current density dependence from your stress results using Black's Law? If not, what values do you use?
4. How do you use the EM data in design and layout rules? (E.g., are reservoirs required, are there length and width dependent rules...?)
5. Do you attempt to normalize results between different technologies? If so how?
6. What is your primary stress method to test for electromigration (E.g., module level vs wafer level, and conditions)?
7. Do you use wafer-level testing
   1. for in-line control?
   2. for lifetime stressing?
8. Have you tested structures built with the dual damascene technique? If so, have you varied your testing techniques at all?
9. Have you had any experience with Cu metallization?
   1. Deposition method of the Cu?
   2. Line definition (E.g., RIE vs Damascene)?
10. Do you expect different failure mechanisms in damascened lines vs in RIE?
11. Do you anticipate any differences in behavior or mechanisms for Cu metallization from what you observed in Al metallizations?
12. Do you use, or intend to use the same test procedures for Cu as are used for Al?
13. Do you have concerns about Cu poisoning the chip devices?
14. Have you observed a dependence of lifetime on line width that is similar to Al (increases with smaller lines) or different?
15. What questions/concerns do you have about Cu reliability?
16. Any further suggestions for the discussion?

1. What is the oxide thickness range you have experience with (in nm)?
2. What is your preferred way of reliability assessment? Choose one: t_bd, Q_bd, E_bd, other - please specify.
3. What is the breakdown criterion used? Choose one or rank several: hard breakdown, soft breakdown, SILC, V_tshift, g_mshift.
   1. Comments:
4. Do you monitor the leakage current at low voltage during highly accelerated stresses? (Yes or No)
   1. If "No", is it necessary for oxides below 6 nm? (Yes or No)
   2. If "Yes", please describe briefly:
5. Which voltage acceleration plot do you prefer? Choose one: E, 1/E, other.
   1. If "other", please include short description and reference
6. Do you consider highly accelerated wafer level stresses sufficient? (Yes or No)
   1. If "No", are packaged module stresses at lower stress conditions required? (Yes or No)
   2. Comments:
7. Do the projections from med/high level stress represent the correct/worst case result at low voltage despite, e.g., a conduction mechanism change? (Yes or No)
   1. Comments:
8. Which fails are more important: extrinsic or intrinsic (wearout)? (extr. or intr.)
   1. Comments:
9. Does a breakdown of ultra thin oxide affect the device function? (Yes or No)
   1. Comments:
10. Any further suggestions for the discussion?

1. Are you a semiconductor customer (a) or a supplier (b)?
2. What is your primary job function?
3. How would you rate your expertise in (Beginner 0...5 Expert)
   1. ESD - protection design
   2. ESD - technology hardening
   3. ESD - testing
   4. Numerical simulation for ESD
   5. Failure analysis
   6. Generation and metrology of sub-nanosecond pulses
4. What kind(s) of technology(ies) are you involved with?
5. What kind of high current tests are you performing ?
   1. HBM MIL
   2. HBM ESDA
   3. HBM JEDEC
   4. HBM EIAJ
   5. MM ESDA
   6. MM JEDEC
   7. CDM ESDA
   8. CDM JEDEC
   9. SDM ESDA
   10. Transmission Line Pulsing
   11. None
6. What kind of high current tests are you outsourcing ?
   1. HBM MIL
   2. HBM ESDA
   3. HBM JEDEC
   4. HBM EIAJ
   5. MM ESDA
   6. MM JEDEC
   7. CDM ESDA
   8. CDM JEDEC
   9. SDM ESDA
   10. Transmission Line Pulsing
   11. None
7. Are you satisfied with repeatability and correlation ?
   1. Yes
   2. No
   3. Which stress models, technologies, particular cases ?
8. Are you performing (a) or would you perform (b) wafer level ESD tests ?
9. Do you disagree 0 ... 5 fully agree ?

   "Chip scale packages and flip chip assemblies minimize the influence of the package on the ESD-failure threshold."

10. Are the demands for stress models and withstand voltages mainly driven by:
    1. the customers ?
    2. the competition ?
    3. the internal quality policy ?
11. How much protection in which model is sufficient to survive Real World?
    1. Is it increasing or decreasing with time ?
12. What are your and your customers requirements to accept an alternative qualification procedure for ESD ?
13. Did you see reliability problems traceable to ESD ?
14. Please comment on my point of view that the goals of CDM/SDM or whatever should be very fast transient ESD-testing (disagree 0 ....5 fully agree)
    1. to have a test method available that reproduces failure signatures of
    2. field failures, that cannot be reproduced by HBM and MM.
    3. to be able to detect a CDM-sensitive design as early as possible in the process.
    4. to be able to quantify the amount of stress that a device can withstand before it fails with the typical failure signatures independent from the individual test system.
    5. to have a reproducible method for the whole stress scale.
    6. to have a test method and standard available that complies with the rules of physics and can thus be adapted to the tools (oscilloscopes, etc.) that are technically available.
15. How important is or will modeling and numerical simulation of ESD be for your company ? (Not even thinking about 0 ... 5 extremely )
16. Can you contribute case studies in any of the above topics to the workshop ?
    For a fruitful discussion, they are highly appreciated, independent of the level of expertise.
    Please, could you provide material in advance? (Even published!)
17. Any further suggestions for the discussion?

1. Have you used, or considered using, any of the following measurement techniques based on C-V measurements?
   1. Conductance Measurements
   2. Capacitance - Time measurements for lifetime analysis
   3. Doping versus Depth computed from C-V Measurements
      1. On Junction Structures
      2. On Oxide Structures
   4. C-V Measurements at other frequencies
   5. C-V Measurements at other frequencies
2. Which of the above measurements did you find useful?
3. Which were not successful?
4. Which other measurement techniques did you try?
5. What problem areas have you encountered during C-V measurements?
   1. Instrument Related
   2. Sample Related
   3. Analysis Related
6. Do you use C-V measurements as isolated measurements or are they integrated and correlated with other measurements in a broad process control strategy?
7. Any further suggestions for the discussion?