The evening discussion group program is regarded as a favorite highlight of
the workshop experience. Attendees will have a choice of 5 topics on both Tuesday
and Wednesday evenings. The same 5 topics will be discussed for 90 minutes each night.
This year's topics are:
1. Fast WLR monitoring: Carole Graas , Infineon Technologies &
Ehren Achee, Centaur Technology
Wafer Level reliability, or WLR, refers to a category of stresses which
are performed by directly applying temperature, voltage, and/or current stress
on specially designed test structures, thus quickly providing data on a wide
range of reliability issues. Because of their flexible design and use, WLR tests
have become pervasive in the Microelectronics
Industry, for applications ranging from technology/process development, to the monitoring of manufacturing lines.
By and large, the success of WLR has resided in its ability to provide
useful data at elevated stress conditions in a very small amount of time (sec to
min), compared to package-level testing. In a fast paced, high volume
development or production environment, stepping from "WLR" to "fast WLR" is
easily done. But what exactly is "fast WLR", and how can it be useful to you —
and your boss?
We hope that by participating in this discussion group, you will come
away with answers to these, and other questions, such as:
· Advantages/disadvantages of fast WLR.
· Isn't WLR fast enough?
· How widely is fast WLR used _ should you switch?
· Use which physical models for the interpretation of fast WLR data?
· Success stories, etc…
2. Burn In: Rolf-P Vollertsen, Infineon Technologies Burn-In is an integral part of IC productions. It serves to screen weak
parts and improve the failure rate during early life. Besides this benefit it is
expensive and it might degrade intrinsic properties by the high stress conditions
or introduce additional fails due to ESD or handling problems. Considerations
on how to reduce Burn-In cost and increase screen efficiency lead to concepts
like wafer level Burn-In or IDDQ measurements. However, the success of
alternative measures depends on the failure mechanism.
The goal of the discussion group is to sample the experience with
Burn-In among the participants, evaluate recent developments and discuss
possible strategy changes to address future needs.
Discussion topics of interest are:
· How effective is Burn-In in general and for certain failure mechanisms?
· What are the risks of Burn-In and how to limit those?
· Why is the usefulness of Burn-In product dependent?
· How can Burn-In be optimized?
· Do we need Burn-In at all and why?
· How to replace or eliminate Burn-In?
· What are the alternatives and do they work reliably?
3. Thin oxides limits: Emmanuel Vincent, STMicrolectronics and
John Suehle, National Institute of Standards and Technology
Characterizing Ultra-thin Gate Dielectrics: Do we know what we are doing ?
Characterizing the reliability of ultra-thin gate oxides presents a new challenge
to quality and reliability engineers. Traditional testing techniques are not applicable
for monitoring and characterizing the integrity and reliability of ultra-thin films.
Discussion topics include:
· soft breakdown detection and physics
· constant voltage vs. constant current testing
· validity of charge-to-breakdown
· intrinsic reliability limits
· SILC
· alternative dielectric materials.
4. Electromigration: Tim Sullivan, IBM Microelectronics and
Harry A. Schafft, National Institute of Standards and Technology
Focal points for discussion will include the following.
· New observations and issues in Al-based metallization, such as
comparison of and/or standardization of structures for
qualification purposes, effects of more complex shapes (e.g., branches), and bridging from one structure to another.
· EM in Cu metallizations; differences from Al, (e.g.,
linewidth dependence, deposition method, etc.); failure criteria, possible pitfalls of
high-temperature testing.
· Wafer level EM for both Cu and Al; effects of different structures on
failure distributions, self-heating, type test algorithm.
· Effects of low-K dielectrics on EM and EM testing.
The intent of the discussion group will be to explore areas of interest to
the participants in a casual environment. The moderators will have material
to stimulate discussion, but no set agenda will be followed.
5. Hot Carriers: Alain Bravaix, ISEM
Hot-Carrier (HC) degradation has been one of the limiting factors for
performance increases in MOSFET's for digital and memory applications. Efforts
to minimize HC degradation have led to new technological processes,
e.g. new drain structures (LDD, LATID, GOLD) and hardened gate-dielectrics (nitrided oxide).
This discussion group will focus on the HC injection phenomena in MOSFET's.
Some of the topics that will be addressed are:
· The impact of some proposed drain structures on reliability.
· Interface trap generation and the charge trapping/detrapping
phenomena under Hot-Hole (HH) injections and Hot-Electron (HE) injections.
· The correlation between transistor degradation and circuit reliability.
· Effect of temperature on the defect generation in the range _40° to
125°C will be discussed.
and Raif Hijab, Cirrus Logic Inc.