INTEGRATED RELIABILITY WORKSHOP
PRELIMINARY PROGRAM
MONDAY, October 18
1:00 _ 8:00 p.m. Lodge check-in. Get room assignment (prearranged) & room key, with lodge area map and information.
(ADA please notify desk of special needs)
1:00 _ 6:00 p.m. Registration: Pick up badges & handout
(Dining Room Lounge)
Discussion Group Assignments / SIG Signup
1:30 _ 3:30 p.m. Tutorial Session #1: "Basic Reliability"
(Angora Room )
"Electromigration"
"Ultra Thin Oxide Breakdown"
"Burn-In"
3:45 _ 5:45 p.m. Tutorial Session #2: "Hot-Carriers"
(Angora Room )
"Simulation, modeling and lifetime
prediction"
"Hot Carrier degradation evolution in deep submicrometer CMOS
technologies"
5:45 _ 6:15 p.m. Registration: Pick up badges and handout
(Dining Room Lounge)
Discussion Group Assignments/SIG signup
6:15 _ 7:30 p.m. DINNER, (Dining Room)
7:00 _ 7:30 p.m. Registration for Late Arrivals (Dining RoomLounge)
7:30 _ 9:00 p.m. Mixer & Poster Session, (Cathedral Room)
9:00 _ 10:00 p.m. SIG Meeting (all SIGs), (Angora Room)
TUESDAY, October 19
6:30 _ 8:00 a.m. Breakfast (Dining Room)
8:15 _ 8:30 a.m. Welcome & Introduction: Eric Snyder, General Chair,
(Angora Room)
Technical Program Overview: William Tonti, Technical Program Chair
8:30 _ 9:30 a.m. Keynote: "Influencing Factors for Consideration of Future Generation System Design"—Benjamin DeLuca, International Business Machines, Austin, Tx
9:30 _ 10:00 a.m. Break
10:00 _ 11:40 a.m. Session #1: Customer Product Reliability Requirements (CPR),
Chairs: Bill Vigrass, Texas Instruments & Rolf-P. Vollertsen, Infineon Tech. Corp.
CPR-1 "A Methodology to Assess the Influence of Burn-In Relating to Long Term Reliability of Submicron CMOS Transistors," CPR-2 "Signal Margin Test to Identify Process Sensitivities Relevant to DRAM Reliability and Functionality at Low
Temperatures," E. Nelson of IBM Microelectronics, Essex Jct. VT; Y. Li, D. Poindexter of IBM Semiconductor R&D Center, Hopewell
Jct NY; M. Ruprecht of Infineon Corp., E. Lim of Semiconductor R&D Center, Hopewell Jct NY; Y. Matsubara, H. Sawasaki
of Toshiba Corp.; Q.Ye of Infineon Corp., W. Tonti of IBM Microelectronics, Essex Jct. VT
CPR-3 "Reliability Aspects of Stress Induced Voiding in
0.25 µm Metallization," A.E. Zitzelsberger, M.U. Lehr of Infineon Technologies
CPR-4 "Reliability Test Results for W FIB Interconnect Structures," M. Zaragoza, Z. Zhang of Cadence Design Systems and 11:40 _ 12:10 p.m. Group Picture
12:10 _ 1:30 p.m. Lunch, Dining Room
2:00 _ 3:40 p.m. Session #2 Reliability Test Structures
(RTS), Chairs: Homi Nariman, Advanced Micro Devices and Tim Sullivan, IBM Microelectronics
RTS-1 "Predicting Plasma Charging Damage to Ultrathin Gate Oxide by Using Nondestructive DCIV Technique," H. Guan, M.F.
Li, Y.H. Zhang, S. Ma, and B.J. Cho of National University of Singapore
RTS-2 "Temperature Gradient Effects in Electromigration Using an Extended Transition Probability Model and Temperature
Gradient Free Tests," K. Jonggook, V.C. Tyree, and C.R. Crowell of University of Southern California
RTS-3 "An Evaluation of Electrical Linewidth Determination Using Cross-Bridge and Multi-Bridge Test Structures," , L.M. Head
of Rowan University and H.A. Schafft of National Institute of Standards and Technology
RTS-4 "Impact of Test-Structure Design and Test Methods for Electromigration Testing," S. Menon of LSI Logic; J. Fazekas, J.
von Hagen of Infineon; L.M. Head of Rowan University; and H.A. Schafft of National Institute of Standards and Technology
3:40 _4:00 p.m. Break
4:00 _ 5:15 p.m. Session #3 Reliability Models A
(RMA), Chairs: Gordon Claudius, Conexant and John Suehle, National Institute of Standards and Technology
RMA-1 "Second Order Thermal Dissipation Effects for Embedded Interconnects," J.P. Gill, D.L. Harmon, J. Furukawa, and
T.D. Sullivan of IBM Microelectronics
RMA-2 "Hot-Carrier Damage In Deep-Submicrometer CMOS Technologies," A. Bravaix, D. Goguenheim of ISEM, and N. Revil,
E. Vincent of STMicrolectronics
RMA-3 "Dependence of HCI Mechanism on Temperature and Direct Tunneling Oxide Thickness for 0.18 µm Technology
and Beyond," W. Wang, J. Tao and P. Fang of Advanced Micro Devices
5:15 _ 6:00 p.m. Poster Session/Late News Papers
6:00 _ 7:30 p.m. DINNER, Dining Room
7:30 _ 9:00 p.m. Discussion Groups,: Chairs: Linda M. Head, Rowan University and Prasad Chaparala, National Semiconductor Corp. 1. Fast WLR monitoring: Carole Graas , Infineon Technologies &
Ehren Achee, Centaur Technology
2. Burn In: Rolf-P Vollertsen, Infineon Technologies and Raif Hijab, Cirrus Logic
Inc.
3. Thin oxides limits: Emmanuel Vincent STMicrolectronics and John Suehle National Institute of Standards and Technology
4. Electromigration: Tim Sullivan, IBM Microelectronics and Harry A. Schafft, National Institute of Standards and Technology
5. Hot Carriers: Alain Bravaix, ISEM
9:00 _ 10:30 p.m. Individual SIG Meetings, Chair: Linda M. Head, Rowan University
WEDNESDAY, October 20
6:30 _ 8:00 a.m. Breakfast (Dinning Room)
8:15 _ 8:30 a.m. Announcements, (Angora Room)
8:30 _ 9:20 a.m. Session #4: Identification of Reliability Effects (IRE),
Chairs: Udo Schwalke, Infineon Technologies and Raif Hijab, Cirrus Logic Inc.
IRE-1 "Conduction Mechanisms in Cu/Low-K Interconnect," G. Bersuker, V. Blaschke, D. Pekker, and W. Wick of Sematech
IRE-2 "A Successful Application of WLR Fast Test on Al Via Process Optimisation," X. Liu, K.F. Lo, Q. Guo, and J. Cai of
Chartered Semiconductor Manufacturing Ltd.
S. Holzhauser and A. Narr of Infineon Technologies AG I.Gr.
M. Abramo of IBM Microelectronics
(90 minute parallel sessions for each topic) Attendees are to participate in one of the five groups: