Tutorials

Tutorials
Tutorial 1 _ Basic Reliability

A. Electromigration—Tim Sullivan, IBM Microelectronics

Electromigration is the electron-flow-induced migration of metal atoms in a conductor, and can lead to resistance increases and failure.Time to failure is generally lognormally distributed, and the median time to failure is related to the applied current density and temperature by Black's equation,
t₍₅₀₎= Aj^-nexp(h/kT). Electromigration has been studied for over 30 years, and considerable understanding of the process has been gained. However, metallization-specific phenomena occur frequently enough to prevent many global generalizations. Structural effects can be large enough to obscure or enhance EM damage. Electromigration testing for a technology is therefore somewhat of an art in which the reliability engineer combines knowledge of physics and electronics with intuition experience to create test structures which will probe the electromigration robustness of a new technology. These structures are tested under accelerated conditions to produce a distribution of failure times, which are then fit to a lognormal distribution, and extrapolated to use conditions. The extrapolated failure time is compared to the business target to determine the allowed current density for the technology.

B. (Ultra)thin oxide breakdown(s), An overview—Emmanuel Vincent, STMicroelectronics, Central R&D Labs

Silicon dioxide layer reliability has always been a major issue for semiconductor manufacturers. In particular the gate oxide breakdown is well known to be one of the potential limiting failure modes affecting the MOS devices. Moreover, as the gate oxide thickness scales from the thin (above 5nm) down to the ultrathin (below 5nm) range, the oxide reliability becomes more and more critical and, before the classical breakdown, novel phenomena appear for ultrathin oxides such as quasi-breakdown events. This evolution, these changes require at least revised, even novel approaches in order to realistically address the ultrathin oxide reliability in deep-submicron technologies.

This tutorial will give a general overview of the breakdown phenomena in thin and ultrathin SiO₂ films highlighting the behavior differences between both thickness ranges and their impact on the ultrathin oxide reliability. The following items will be addressed:

Testing methodology

Physical understanding of the failure mechanisms

Extrapolation modeling

C. Burn-In—Rolf-P Vollertsen, Infineon Technologies Corp.

Burn-In is used to screen weak parts from a population of completely processed chips. Thereby it helps to meet reliability requirements. This tutorial will provide a general introduction to Burn-In. It will show how Burn-In improves the failure rate and in which cases it is useful. The benefits and disadvantages will be addressed as well as the Burn-In conditions, models and failure mechanisms. There will be a section discussing the impact of Burn-In on technology reliability (hot carriers, gate oxide, electromigration). Frequently the upper limits of the Burn-In conditions are controlled by technology reliability.

Tutorial 2 _ Hot Carriers:

A. Hot Carrier Degradation evolution in deep submicrometer CMOS technologies—Alain Bravaix, ISEM

Since the beginning of the seventies, the performance increase of microelectronics industry has been obtained mainly by decreasing the size of circuit features. This strong miniaturization obtained by process optimization and technology improvement has imposed to change the circuit scaling scheme as device reliability is become a major challenge. Hot-Carrier (HC) degradation has been one of these limiting factors in MOSFET's for digital and memory applications which has led to new technological processes, e.g. new drain structures (LDD, LATID, GOLD) and hardened gate-dielectrics (nitrided oxide). For the new generation technologies, DC lifetime evaluation obtained on single devices needs to be adapted to the case of real circuits as the interaction between the different damage mechanisms complicate the evaluation of the resultant damage during AC operations. This tutorial will address the following topics:

1. HC injection phenomena in MOSFET's will be reviewed focussing on the different degradation behaviors in N- and P-channel MOSFET's.

2. The impact of some proposed drain structures on the HC reliability will be discussed. Emphasis will be put on AC alternating stress conditions in order to assess the role of the interface trap generation and the charge trapping/detrapping phenomena under Hot-Hole (HH) injections and Hot-Electron (HE) injections.

3. The correlation between transistor degradation and circuit reliability will be discussed based on duty-cycle calculations focussing on the gate-oxide thickness (T_ox) reduction for digital applications. Hence, the degradation of inverter and ring oscillators will be investigated which exhibit new competitive damage mechanisms.

4. The particular case of pass transistor degradation used in SRAM cells will be further analysed as it represents a more severe case than the two latter circuits.