CMOS IC Reliability Assessment for Government Applications
I will present an overview of the work my organization is doing in support of the DARPA "IRIS" Program. Our work focuses on developing the technology to predict the long-term reliability of COTS Ics (both Digital and Analog Mixed Signal) from a very limited sample set (≤ 10 chips). We focus on wear-out or “aging” related reliability effects including negative-bias-temperature-instability (NBTI), time-dependent-dielectric-breakdown (TDDB), and hot carrier (HC). A three-prong approach is used in our prediction methodology: 1) building better wear-out models for select CMOS technologies using experimental reliability data, 2) building custom reliability circuit simulation tools to apply these models to IC test articles, 3) Developing “in-situ” testing methods to acquire reliability data from COTs Ics (without the use of custom reliability test circuits). The ultimate goal is the development of efficient methods for evaluating mean-time-to-failure of COTs Ics from very limited sample sets.
Michael Fritze leads ISI’s Disruptive Electronics organization, which seeks to leverage novel electronics technologies and architecture concepts to create new capabilities in fields such as space electronics, embedded computing, trusted electronics and high performance computing. His organization focuses on CMOS extensions and post-CMOS concepts, radiation-hardened electronics, reliable & robust electronics, 3DIC technology, low power electronics and carbon electronics. An established researcher and former program manager at the Defense Advanced Research Projects Agency (DARPA), he conceived, developed, obtained funding for, and managed diverse programs in low-power and radiation-hardened electronics, micro-fabrication, foundry access, and radio frequency electronics. Fritze also created cost-effective partnerships with CMOS foundries that provided the Department of Defense with state-of-the-art electronics technologies access. He earned his Ph.D. in physics in 1993 from Brown University and B.S. in Physics in 1984 from Lehigh University. Prior to his DARPA term, Dr. Fritze was a researcher at MIT Lincoln Laboratory in the field of SOI-based microelectronics.
Investigating the High-k/InGaAs MOS System for Future Logic Applications
As silicon devices reach the limit of dimensional scaling there is a growing interest in the use of high electron mobility channels, such as InxGa1-xAs, in conjunction high dielectric constant (high-k) gate oxides in future n-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). The understanding and control of electrically active defect states at the high-k/InxGa1-xAs interface and of charges within the atomic layer deposited (ALD) high-k films will be essential for the successful implementation of high mobility channel materials. The objective of this presentation will be to provide an overview of the current understanding of the density and distribution of electrically active defects at the high-k/In0.53Ga0.47As interface. The presentation will also consider defects located in the interfacial transition region between the high-k oxide and the InGaAs channel which are manifest as hysteresis in the capacitance-voltage response. Finally, the paper will present preliminary results which indicate the reliability of the high-k/InGaAs MOS system can be improved by the use of forming gas annealing performed in-situ following the high-k deposition.
Dr. Hurley received his Ph.D. (1990) and B.Eng. (1985, 1st class honors) in Electronic Engineering at the University of Liverpool. Paul is a currently Senior Research Scientist and Head of the Silicon Research Group at the Tyndall National Institute at University College Cork. Paul leads a research team of ten PhD students, post-doctoral researchers, visiting students and Tyndall Research staff who perform basic research on high dielectric constant (high-k) thin films for applications in nanoelectronics, where the current research work is focused on the use of high-k in conjunction with III-V semiconductor materials for future logic devices. Paul received an Intel Outstanding Researcher award for his work in high-k/III-V interface defect studies in 2012. Paul is a member of the Technical Committee of the Insulating Films on Semiconductors (INFOS) conference and the International Workshop on Dielectrics in Microelectronics (WoDiM). In addition to research activities, he is a part time lecturer in the Department of Electrical Engineering at University College Cork. He has published over eighty papers in the field of micro and nanoelectronics, and has given over 20 invited presentations and seminars in the high-k area from 2006 to 2012.
Understanding Operation and Reliability in HfOx RRAM Devices through Physical Modeling
In this paper we investigate the physical mechanisms governing the operations and the reliability in HfOx RRAM devices using a physical model which describes self-consistently the charge transport (including trap-assisted-tunneling, Poole-Frenkel, drift, etc.), the associated power dissipation and temperature increase, the temperature- and field-assisted generation, diffusion and recombination of oxygen vacancies and ions. Model parameters, related to material and interface properties, are derived from ab-initio calculations, molecular dynamics and ad-hoc experiments. Simulation results allow understanding at quantitative level the physical mechanisms occurring during forming, set and reset operations, and those responsible of reliability (read disturbs, retention, endurance) and variability (noise, cycle-to-cycle variations)in HfOx RRAM devices.
Luca Larcher graduated in Electronic Engineering from the University of Padova, Italy, in 1998. In 2001 he was appointed Assistant Professor at the University of Modena and Reggio Emilia, where he is currently Associate Professor of Electronics since the 1st of November 2005. He received his Ph.D. degree in “Information Engineering” from the University of Modena and Reggio Emilia in 2002. He has joined and leaded research projects in collaboration with international research centres and companies, supported by regional, national and European programs. He authored and co-authored a book, more than 140 technical papers published on international journals and proceedings of international conferences. He has joined the technical committees of the IEEE-IEDM (2006-2007) and IEEE-IRPS (2011-2012) conferences.
Atomic Scale Defects in MOS Reliability Problems
A fundamental atomic scale understanding of the physical mechanisms involved in solid state device reliability problems has long been an important goal among reliability researchers. This is so because such an understanding can lead to an amelioration of the problems or at least help in the development of reliable predictive models. Several magnetic resonance techniques have both the sensitivity and the analytical power to detect and identify the atomic scale defects in important MOS reliability problems such as the negative bias temperature instability (NBTI) as well as hot carrier effects and radiation damage. Resonance techniques can also identify defects in high-k MOS systems and, more broadly, in time dependent dielectric breakdown (TDDB). Quite recent advances in electrically detected magnetic resonance (EDMR) allow resonance measurements to be combined with standard purely electrical characterization techniques such as charge pumping. The results of magnetic resonance studies of these reliability problems has lead to the identification of some, perhaps nearly all, of the atomic scale defects involved. In this presentation I will discuss atomic scale defects involved in several MOS reliability problems including NBTI, radiation damage, and instabilities in high-k devices and some discussion of TDDB defects. I will also discuss the physical mechanisms involved in the population and creation of the defects as well as physically based reliability models. Since most of the presentation will deal with magnetic resonance results, I will also include a brief tutorial introduction to several magnetic resonance techniques with special emphasis placed on new zero field and low field EDMR.
P.M. Lenahan earned his B.S. degree from the University of Notre Dame and his Ph.D. from the University of Illinois, Champaign-Urbana. After completing his Ph.D. in 1979, he was a post-doctoral fellow at Princeton University in 1979 and 1980. From 1980 until 1985 he was a member of the technical staff in the Materials Research Directorate of Sandia National Laboratories in Albuquerque, New Mexico. Since 1985 he has been at Penn State University where he is Distinguished Professor of Engineering Science and Mechanics (ESM) and Co-Chair of the Inter- College Program in Materials. ESM is the materials engineering and applied physics department of the Penn State Engineering College; the department also operates an honors degree program for engineering students interested in applied physics. In 2001, he was visiting professor of Electronics and Computer Engineering at Nihon University, Tokyo, Japan. (Nihon University is the largest university in Japan.) He has authored over 150 publications in refereed journals, approximately 275 conference presentations, and two patents. The publications and patents have been cited about 4000 times in the scientific and technical literature. His research has been primarily focused upon the trapping centers which limit the performance of semiconductor devices. Dr. Lenahan has served as the technical program chairman (2007) and the general program chairman (2008) of the IEEE IIRW. He is a fellow of the IEEE.
A Novel Strategy for Ideal MOS Stack of High Dielectric Reliability: Preventing Leakiness of the Thatched Roof to keep the Tatami Comfortable
We review our recent experimental results on the hydrogen (H) impurity diffusion behavior in MOS structures that suggest a new approach to improve their dielectric reliability. The most desirable MOS stacks feature a specific oxynitride cover in an upper layer that prevents H impurity leaking into the dielectric films underneath.
The hydrogen diffusion behavior in intact model MOS stacks as well as in the basic SiO2/Si system is probed by H depth profiling via resonant 15N-H nuclear reaction analysis combined with a variety of surface-sensitive spectroscopies. It is found that almost all thin film materials that comprise the MOS devices are permeable to H impurities. Diffusion of the latter, however, can be suppressed by a specific ultra-thin oxynitride layer, which has exceptionally stable H-storing properties. Since the degradation of MOS devices was demonstrated to correlate with H accumulation in the oxide/Si interface region, we suggest that not merely the well-investigated buried SiO2/Si interface but also the top surface of the MOS stack is of critical importance for the reliability. In other words, guarding the entire MOS stack from H-related impurity diffusion (such as by an H-retaining oxynitride interlayer) will be instrumental in realizing highly reliable dielectric films.
Ziyuan Liu received the M. S. degree from Materials science and engineering, Beijing Institute of Aeronautics, Beijing, China, and the Dr. Sc. degree from Material Science, Tokyo Institute of Technology, Tokyo, Japan. She joined the NEC Corporation in 1997, and is currently a chief professional at Device & Analysis Technology Div. in Renesas Electronics Corporation. She is responsible for the development of device analysis technologies, thin films analysis technology, and monitoring methodologies for manufacturing process. She joins the collaboration of Renesas Electronics Corp. with University of Tokyo, and where investigates the behavior of hydrogen impurity (H) in silicon dioxide, nitride films and the MOS electrode/dielectric stacks, and their relation to the reliability issue of the Si-devices including the flash EEPROMs. Dr. Liu has served as a member on the Gate Dielectric Reliability Committee for 2011, 2012 and 2013 International Reliability Physics Symposium (IRPS). Her research interests include the dielectric reliability physics, and film surface engineering.
Reliability Testing and Test Structure Design in an Age of Increasing Complexity
Two challenges of semiconductor device scaling are: 1) process complexity increases with each generation 2) variability increases with device scaling. The impact of 1) is clear to anyone involved in early process development, when apparently trivial changes in process for high-k metal gate stacks can lead to significant changes in such reliability characteristics as BTI time slope, magnitude, and recovery, all often treated as universals in reliability literature. Almost by definition 2) could be considered most challenging in reliability relative to other area of semiconductor engineering because in practice semiconductor reliability is the study of spatially and temporally rare events often involving one or several atoms. The two challenges are intimately linked because when advanced process node features such as stress liners, stress memorization and raised source/drains play a role in device performance, the channel length/width become only one piece of the layout induced variability. These challenges drive the need for faster reliability measurements done in higher volume. Testing can be done on individual devices with several SMUs, through simplified decoder structures with thousands of devices, to full product level using very expensive APGs. We discuss some of the engineering and (necessarily) economic choices that drive the techniques and structures used for electrical measurements made at each of these levels.
William McMahon received his PhD in Physics from the University of Illinois at Urbana-Champaign. His PhD research focused on atomic-scale models of intrinsic reliability degradation mechanisms. He worked for several years at the Data Storage Institute in Singapore on various forms of spin transport in ferromagnetic materials. He subsequently worked at Intel/Numonyx on reliability and device characterization for NOR flash memory, in particular focusing on SILC and random telegraph noise. He forsook the commoditized non-volatile memory market to work for GlobalFoundries on various aspects of high-k metal gate reliability, currently on FinFETs at the 14nm technology node. His most recent primary focus has been on techniques to optimize learning of process impact on reliability mechanisms and variability.
David J. Meyer
Assessment of GaN High-Electron-Mobility Transistor Reliability for RF Amplifier Applications
As an electronic material, GaN possesses several material advantages over conventional III-V semiconductors that lead to an order of magnitude improvement in transistor RF output power density. The maturity of GaNamplifier technology is currently a topic of significant interest in the DoD community as several system insertion opportunities are emerging. Serving as an objective validator of GaN amplifier technology delivered to the government, NRL plays a key role in assessing RF performance and reliability to provide feedback to both government entities and contractors. To complete this task, we use a suite of dc, RF, and pulsed I-V electrical testing to identify and monitor electrical degradation of monolithic microwave integrated circuits (MMICs) as a function of time. In our most basic testing, MMICs are biased under normal operating conditions (with peak channel temperatures between 150 °C and 225 °C) and monitored for 1000 – 3000 hours. Nearly all GaN technology delivered by contractors today will experience no electrical degradation during this RF operational life-test, but the question still remains: Are these amplifiers reliable for the lifetime of a system? To address this question, we routinely use elevated temperature(channel temperatures between 300 °C and 375 °C) RF life-testing to accelerate failure mechanisms and determine lifetime at typical operating temperatures via Arrhenius extrapolation. Post-stressed, parametrically failed devices are subjected to failure analysis using a variety of materials characterization techniques, such as focused-ion-beam cross-sectioning, transmission electron microscopy, energy dispersive spectroscopy for elemental analysis, etc., in order to correlate changes in electrical behavior to physical degradation mechanisms. In this talk, an overview of our testing methodology will be presented, along with discussion about degradation mechanisms that are observed in GaN transistors.
Dr. Meyer received his B.S. degree in Electrical Engineering in 2003 from Pennsylvania State University, where he continued on to obtain a M.S. degree in Engineering Science in 2004 and then a Ph.D. degree in Materials Science and Engineering in 2008. His Ph.D. research focused on understanding and improving SiN passivation of GaN high-electron-mobility transistors (HEMTs). After graduating, he continued in the field of GaN transistor research by joining the Microwave Technology Branch of the Naval Research Laboratory (NRL) in Washington, DC. Serving as the team lead for several GaN HEMT related projects, Dr. Meyer's research at NRL has aimed at pushing the frequency and power performance of GaN HEMTs to new frontiers through geometric scaling and novel heterostructure design. He has authored or co-authored over 25 journal articles, 45 conference presentations, and 1 patent in this field. In addition to in-house research, Dr. Meyer also directs the efforts of the GaN reliability testing laboratory at NRL, which performs independent validation and verification of government contractor deliverables based on GaN technology.
Reliability Concerns of Yesterday – Emerging Memory Cells of Tomorrow?
This talk will highlight how we are eager to embrace phenomena that were considered catastrophic reliability concerns until recently, and "optimize" them to create memory cells for potential replacement of conventional NAND, NOR and DRAM cells. If you cannot fight them, join them! Few examples are (a) defect percolation-path induced dielectric breakdown - conductive bridge filamentary cells in RRAM; (b) device snapback - capacitor-less DRAM thyristor memory cells (TRAM); (c) e-p generation/impact ionization - floating body capacitor-less DRAM (FBE); (d) localized high-current, joule heating - phase change memory; (e) oxygen vacancy migration - metal oxide/CMO RRAM.
There are several challenges in working with and optimizing phenomena that are generally considered chaotic and random in nature. This talk will discuss practical issues like noise - RTS, drift in retention, stuck bits, error correction needs etc. in emerging memory technologies.
Chandra Mouli is with Micron Technology Inc., Boise, ID, USA. He is currently Director of Device Technology with responsibilities in the area of advanced device characterization, reliability analysis, test structure design/layout, process & device modeling for all technologies under development in R&D. He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science (IISc), Bangalore, India and Ph.D (EE) from the University of Texas at Austin. He was with Texas Instruments for couple of years before joining UT/Austin. His interests include semiconductor devices and process technology for advanced memory, opto-electronic devices, exploratory research in the area of new materials and device structures. He has more than hundred issued patents and several pending in various areas of semiconductor devices and process – in advanced memory, novel devices and image sensor technology. He has served in the technical committees for various conferences, including IEDM, IRPS and SISPAD. He has also served in the review committees for NSF and SRC. He is currently a member of the scientific advisory board in SRC’s focus center programs and is a member of the ITRS technical working group.
If interconnects do not scale with advancing technology, what is there to say about reliability?".
Back-end-of-Line (BeoL) Reliability has been a major concern at least since electromigration (EM) was first identified in the late 1960s as a critical failure mechanism within integrated circuits. Typically, reliability concerns arose because simple technology scaling placed larger current density demands on the metallization system. To slow down the erosion of reliability margin with scaling, Cu metallization using Dual-Damascene (DD) integration was introduced around the 180/130nm node. In addition, low-k dielectrics (2.5 <~ k <~ 3.0) were later incorporated into DD integration schemes to keep in check the negative impact of of interconnect RC delay.
The canonical DD integration approach has been very successful down to around 45/40nm; however, as technology development continues beyond 32/28nm, the benefits of materials scaling are evidently showing diminishing returns. There are several reasons:
(1) The resistivity of Cu metallization becomes increasingly unacceptable with scaling as grain boundary and interface scattering effects dominate;
(2) Ultra-low-k dielectric (ULK, k <~ 2.5) incorporation is a potential reliability concern because non-localized porosity intrinsically worsens time-dependent dielectric breakdown (TDDB) performance;
(3) Cu EM performance cannot maintain reliability margin with additional scaling and without major process enhancements.
Such process improvements have been observed to worsen interconnect metal resistivity and potentially negates at least (or does not help at all) some of the expected benefits of device performance improvement associated with the incorporation of high-k/metal gate and FinFET transistor technologies. Thus, the cost/benefit calculations associated with stagnating performance of Cu/LK BeoL integration should factor into the ability to scale interconnects beyond 7 nm, especially if the prototypical Cu/ULK solutions cannot handle increased performance demands needed for scaling. Thus, if interconnect scaling cannot be readily not done, what will be the consequences for interconnect reliability?
Ennis T. Ogawa is currently Senior Principal Reliability Scientist in the Quality and Reliability Assurance Department at Broadcom Corporation in Irvine, CA. He received his Bachelor of Science degree in physics from Stanford University (1986) and his Ph.D. in physics at The University of Texas at Austin in the field of high temperature superconductivity (1994). Following his doctoral degree, he worked as a postdoctoral fellow in the Interconnect and Packaging Lab, directed by Professor Paul S. Ho, at The University of Texas at Austin and continued as a Research Associate until mid-2001. His research interests there focused on the thermal conduction of low-k polymers, metal-polymer adhesion, low-k materials characterization, interconnect thermal stress, and Al(Cu)-based and Cu-based electromigration. He later worked at Texas Instruments in Dallas, TX, where he focused on the reliability of Cu/low-k backend advanced Si technologies such as electromigration, stress-induced voiding, intermetal and interlevel dielectric reliability, and thermal management. At Broadcom, he presently directs foundry process reliability and qualification for advanced technologies and works on detailed reliability assessment of Broadcom designs and products, primarily but not exclusively in back-end reliability. He has previously served on the Technical and Management Committees at The International Reliability Physics Symposium (IRPS) and was General Chair in 2012. He is now IRPS-2013 Board of Directors Chair. He currently holds 5 patents and is an author of 39 journal and/or technical conference papers and three book chapters on reliability in advanced CMOS-based technologies.
Device Degradation Models for Circuit Reliability Simulation
With reliability margins shrinking, it is increasingly important to carefully assess the impact of device degradation during circuit design. Circuit reliability simulation is a very useful tool for this purpose as it allows designers to guarantee that circuits are sufficiently robust against device degradation, while they are not bound by overly robust design rules. Hence its usage is becoming more and more widely adopted in mixed signal circuit design. Various degradation mechanisms can be evaluated using circuit reliability simulation including hot carrier degradation, NBTI, PBTI as well as TDDB.
In this paper I will present the underlying models that are available to describe device degradation as a function of stress conditions. I will explain the methodology used for translating DC degradation models to the time varying stress signals encountered in actual circuits as well as the justification and the limitations of adopting this approach. I will discuss standard CMOS as well as bipolar and DMOS transistors.
Guido T. Sasse received his M.Sc. and Ph.D. degree in Electrical Engineering from the University of Twente, Enschede, The Netherlands in 2003 and 2008 respectively. He performed his Ph.D. research at the MESA+ institute for nanotechnology, where he studied RF CMOS reliability, reliability simulation and the development of new CMOS (RF) characterization techniques. After obtaining his Ph.D. degree, he joined NXP Semiconductors, Nijmegen, The Netherlands, where he is currently a principal reliability engineer. His activities are primarily focused on front-end related reliability topics; this includes process qualification, providing reliability support to wafer fabs and circuit designers as well as the development of models for reliability simulation.
Impact Factors for BTI Lifetime Prediction
Today Bias Temperature Instability is the most prominent device degradation mechanism of MOSFETs. A big part of currently published reliability papers deal with BTI. The detailed degradation mechanism behind is still under discussion. Exploration is on-going.
However, for lifetime predictions for transistors or complete products, the daily work of reliability engineers of semiconductor companies, it is only secondarily if reaction/diffusion or switching traps are the correct microscopic mechanism. A lot of other aspects play important roles for accurate BTI lifetime extrapolations. Detailed requirement profiles, proper test-structures, accurate measurement techniques, correct consideration of recovery, and a deep understanding of circuit functions and more are impact factors for a safe and accurate reliability assurance. My talk will address these issues for BTI lifetime predictions. It will discuss both, hazards like adulterant influences of measurement delay or PID of test-structures as well opportunities like the s-curve behavior of AC-stress. Finally, some simple guidelines are set up.
Dr. Christian Schlünder has received his Dipl.-Ing. (1999) in electrical engineering and his doctoral degree in engineering science (2006) accompanying his regular work (both from the Technical University of Dortmund, Germany).1999 he joined Infineon as a member of the Corporate Research Department. In the year 2000 he changed to the Corporate Reliability Methodology Group. Today, as a Senior Staff Engineer, he manages technology qualification and quality assurance for various state-of-the-art CMOS & Smart-Power-Technologies.Christian Schlünder authors / co-authors more than 45 papers in various conference proceedings and microelectronic journals. Furthermore he has written a book chapter on Hot Carrier Stress in different circuit applications. Additionally, he has presented invited talks and tutorials at many conferences such as ‘IRPS’, ‘ESSDERC’, ‘DATE’ or “ZuE”. He is frequently a member of the Technical Program Committee of the IEEE-conferences ‘IRPS’ and referee for several microelectronic journals.
Degradation and Reliability of Silicon Power Transistors
The degradation of silicon power transistors (RESURF LDMOS type) are studied under high voltage off-state and on-state stress conditions. The deterioration of the devices is shown to be hot-carrier dominated. Hot carrier damage occurs at the drain side of the drift region and leads to changing I-V curves in two distinct regimes. With a non-invasive low-voltage leakage characterization the surface generation velocity profiles after stress can be extracted. These enable predictions of the I-V behaviour across a wide temperature range, and may be used for reliability projections of these devices.
Jurriaan Schmitz was born in Elst (NL) in 1967. He received his M.Sc. (with honors) and Ph.D. in experimental physics from the University of Amsterdam in 1990 and 1994, respectively. He joined Philips Research (NL) in 1994 as Senior Scientist to work on CMOS device technology, characterization and reliability. In 2002 he left Philips to become full professor at the University of Twente (NL) where he presently heads the Department of Electrical Engineering. He (co)authored over 200 scientific papers and 18 patents. His research interests include CMOS post-processing, novel silicon device concepts, wafer-level electrical characterization of devices, and device and material reliability.
Prof. Schmitz is an executive committee member of IEEE IEDM and Editor of IEEE Electron Device Letters.
Radiation Effects and Reliability: Physical Mechanisms and Rate Prediction
The reliability challenges for semiconductor devices change significantly as technology scales and new materials are introduced. One of the most important reliability challenges is soft errors produced by ionizing particles. For terrestrial applications, secondary particles produced by neutron interactions and alpha particles emitted from packaging and back-end-of-line materials are the main concerns. Detailed understanding of the physical mechanisms responsible for radiation-induced charge generation is required to predict the rate at which errors will occur. Parametric degradation produced by electrical stress or long-term exposure to ionizing radiation also is an important issue. The physical mechanisms responsible for device-level effects are in some cases similar for radiation-induced degradation and electrically-induced degradation. In particular, interface traps and oxide charge can be generated by either energetic carriers produced by gate and drain biases or by radiation-induced ionization. These effects often involve hydrogen. Shifts in threshold voltage, transconductance, and other device parameters occur in both MOSFETs and HEMTs, but the details depend on the specific defects responsible for the degradation. Methods of predicting the soft-error rate and the stress-induced degradation rate are discussed.
Ron Schrimpf is the Orrin Henry Ingram Professor of Engineering and Director of the Institute for Space and Defense Electronics at Vanderbilt University. He received his Ph.D. degree in Electrical Engineering from the University of Minnesota and he was a professor at the University of Arizona before joining Vanderbilt. Ron was an invited professor at the University of Montpellier in 2000. Ron's research focuses on radiation effects and reliability in semiconductor devices and integrated circuits. He has served as Chairman of the IEEE Radiation Effects Steering Group and General Chair of the IEEE Nuclear and Space Radiation Effects Conference. Ron has published more than 400 papers in refereed journals and has edited two books on radiation effects and defects in semiconductors. He has received Outstanding Paper Awards at the IEEE Nuclear and Space Radiation Effects Conference, the IEEE Industry Applications Conference, and RADECS.
Modeling Reliability of GaN HEMTs
Gallium Nitride material system is becoming the fastest growing technology platform for applications in microwave power devices. The large band gap, strong piezoelectric property and the ability to achieve very high sheet electron density in HEMT configurations has been mainly responsible for their widespread study and use. However, this technology does suffer from various reliability concerns. The three main reliability concerns in GaN HEMTs are (1) electromechanical coupling, thermal performance of the technology and the (3) charging and discharging of surface trap states via Poole-Frenkel conduction. To address these three issues, a comprehensive electrothermal particle-based device simulator was developed at Arizona State University and the results of these investigations will be presented at the conference. Future work in this area will be discussed as well.
Dragica Vasileska received the B.S.E.E. (Diploma, equivalent to M.S. Degree in USA) and the M.S.E.E. Degree form the University Sts. Cyril and Methodius (Skopje, Republic of Macedonia) in 1985 and 1992, respectively, and a Ph.D. Degree from Arizona State University in 1995. From 1995 until 1997 she held a Faculty Research Associate position within the Center of Solid State Electronics Research at Arizona State University. In the fall of 1997 she joined the faculty of Electrical Engineering at Arizona State University. In 2002 she was promoted to Associate Professor and in 2007 to Full Professor. Her research interests include semiconductor device physics and semiconductor device modeling, with strong emphasis on quantum transport and Monte Carlo particle-based device simulations. She is a Senior Member of both IEEE and APS. Prof. Vasileska has published more than 160 publications in prestigious scientific journals, over 80 conference proceedings refereed papers, has given numerous invited talks and is a co-author on two books: Computational Electronics, D. Vasileska and S. M. Goodnick, Morgan & Claypool, 2006; Computational Electronics: Semiclassical and Quantum Transport Modeling, D. Vasileska, S. M. Goodnick and G. Klimeck, CRC Press, 2010. She is also an editor of two books: Cutting Edge Nanotechnology, In-Tech, 2010 and Nano-Electronic Devices: Semiclassical and Quantum Transport Modeling (Co-Editor S. M. Goodnick) Springer, July 2011. She has many awards including the best student award from the School of Electrical Engineering in Skopje since its existence (1985, 1990). She is also a recipient of the 1998 NSF CAREER Award. Her students have won the best paper and the best poster award at the LDSD conference in Cancun, 2004 and the best oral presentation award at the ISDRS Conference in 2011. Dragica Vasileska is a Senior Member of IEEE.
Ernest Wu and Jordi Suñé
Recent Advances in Dielectric Breakdown of Modern Gate Dielectrics
In this talk, we will focus on the recent advances in theoretical and experimental of voltage and temperature dependence of dielectric breakdown for model gate dielectrics including high-k/SiO2 stack dielectrics. Unlike previous accepted notions, we will provide experimental evidence using large sample size and fast-time resolution experiments to show that first-BD statistics follows two-parameter Weibull distribution analogous to SiO2. On the other hand, progressive-breakdown time and residual-time distributions for high-k/SiO2 stacks are found be bimodal and significantly different from those of SiO2. With this new and common framework of first BD statistics for either high-k/SiO2 dual-layer or SiO2 single-layer dielectrics, we discuss the recent results of a hydrogen release-reaction model for voltage and temperature dependence of time-to-breakdown. Although hydrogen-release model has been proposed on empirical or semi-quantitative theoretical basis for a while, recent work in the framework of two-step model which includes both hydrogen release from the anode interface and defect creation reaction in the insulator bulk, provides a quantitative explanation for three outstanding experimental observations: (1) the decrease of voltage acceleration exponents with increasing temperature, (2) the non-Arrhenius temperature dependence at low voltages, and (3) the large activation energy of ~1.0eV observed at high temperatures.
Ernest Y. Wu is a senior technical staff member at Semiconductor Research and Development Center (SRDC) in IBM Microelectronics Division. He is responsible for technology qualification and development of dielectric reliability methodologies including advanced high-k and low-k dielectrics. Dr. Wu has served on the device dielectric committee as chair and co-chair for 2007 and 2005 International Reliability Physics Symposium (IRPS), respectively. He is a member of CMOS and Interconnect Reliability committee of International Electron Device Meeting (IEDM) for 1999 and 2000. He has authored and co-authored more than 100 papers in technical journals and international conferences with several invited papers and tutorials as well as 15 IEDM papers. He has co-authored two books on gate dielectric reliability entitled “Reliability Wearout Mechanisms in Advanced CMOS Technologies” and “Defects in Semiconductors”. In 2004, he received IBM Outstanding Technical Achievement Award for contributions to ultra-thin gate reliability in advanced CMOS technology. His research interests include dielectric reliability physics, device physics and simulation.
Assessing the Reliability and Performance Impact on the Three-Dimensional Structure of Multigate Field Effect Transistor (MugFET)
Multigate Field Effect Transistors (MugFETs) have begun to enter the marketplace, and therefore, have garnered significant attention. This is due the outstanding attributes of these three-dimensional device structures, which include excellent immunity to short channel effects, and CMOS compatible processing. However, there are some unique aspects to this type of device structure that should be investigated to ensure their viability to extend to future nodes. The goal of this presentation is to show electrical characterization and reliability evaluation approaches that provide an overview of MugFET device aspects and how they impact reliability and performance. The focus will be on silicon-on-insulator, double-gate MugFETs also known as a type of FinFETs.
Chadwin D. Young received his B.S. degree in Electrical Engineering from the Univ. of Texas at Austin in 1996 and his M.S. and Ph.D. in EE from the North Carolina State University in 1998 and 2004, respectively. In 2001, he joined SEMATECH where he completed his dissertation research on high-k gate stacks and continued this research at SEMATECH as a Senior Member of the Technical Staff working on electrical characterization and reliability methodologies for the evaluation of high-k gate stacks on current and future device architectures. He has recently joined (09/12) the Materials Science and Engineering Department at the University of Texas at Dallas as an Assistant Professor where his research focus is on electrical characterization and reliability methodologies for the evaluation of future materials and devices. He has authored or co-authored 195+ journal and conference papers. He has served: on the management or technical progam committees of IIRW, IRPS, SISC, IEDM, WoDiM; as Guest Editor for IEEE Transactions on Device and Materials Reliability; and as a peer reviewer for several journals. He is currently a Senior Member of IEEE.