From COTS to Space Grade Electronics – Improving Reliability for Harsh Environments
After a brief overview of the aerospace radiation environment and how chronic accumulated radiation exposure (total ionizing dose and neutron/proton dose) and single-event effects (SEEs) plague electronics, we will consider the unintentional improvements in radiation hardness that have evolved as a natural consequence of technology scaling. This “natural” hardening is one of the reasons for the growing use of consumer-off-the-shelf (COTS) parts in aerospace systems that once used exclusively military and space-grade hardware. We then focus on the various screening, lot-control, and custom packaging methods used by manufacturers to offer higher reliability over extended temperature ranges for components used in intermediate aerospace applications. Finally we conclude with an overview of the process technology, design, and architectural approaches to mitigate radiation effects in commercial rad-hard electronics that are qualified for use in mission-critical aerospace applications.
Robert Baumann received a B.A. in Physics (cum laude, ‘84) from Bowdoin College and a Ph.D. in Electrical Engineering from Rice University (‘90). He joined Texas Instruments in 1989 where he discovered that the reaction of 10B with low-energy neutrons from the cosmic-ray background was responsible for the majority of reliability failures in most digital electronics and developed several mitigation schemes. From 1993-1998 he worked in TI Japan on DRAM/CPU reliability and created an advanced failure analysis group focused on providing short-cycle critical analyses for solving high-profile manufacturing problems. In 1998 Robert returned to TI Dallas where he developed the TI radiation effects program for advanced digital technologies. He co-led the SIA-appointed experts panel that was directly responsible for 2007 changes to ITAR that greatly reduced the risk of U.S. commercial electronics becoming inadvertently export-controlled. He was one of the main authors/leader behind the publication of the JEDEC (JESD89, 89A) industry standard for radiation testing of commercial microelectronics for which he was awarded the 2006 JEDEC Chairman’s Award. Robert is currently a TI Fellow in the Aerospace and Defense Product Group, focused on space and avionics radiation effects and the development of a new FRAM optimized for harsh environments. He is an IEEE Fellow and has authored/coauthored > 70 papers, two book chapters, and eight U.S. patents with several more pending.
Scanning Probe Tomography for Advanced Material Characterization
With the introduction of 3D devices and stackable architectures in both logic and memory applications, the physical characterization of 3D nano-sized volumes is becoming of paramount importance. Furthermore, for specific applications the characterization cannot be limited to the observation but it also has to incorporate the electrical features of the sample. Therefore the main requirements for a valuable 3D characterization technique are: (1) nano-scale sensitivity for morphological and electrical features and (2) capability to expand from 2D (surface analysis) towards probing in the three dimension. In this work we propose conductive atomic force microscopy (C-AFM) tomography as an approach for three-dimensional characterization. In essence we combine the high lateral-resolution of conventional C-AFM to our wear-resistant diamond-tips. With C-AFM tomography we slice in a controlled manner through the vertical dimension of our sample collecting C-AFM slices at different heights. The collection of slices is than stacked and interpolated for the final 3D-visualization. In C-AFM tomography we can achieve sub-nm material removal-rate which turns this technique into a powerful approach for the physic/electrical characterization of highly confined volumes. In this paper we are going to discuss its application and potentiality in different fields ranging from physical understanding of resistive switching up to failure analysis and reliability of memory devices.
Umberto Celano received his B.Sc. degree in Electronic Engineering in 2009 from Sapienza University of Rome, Italy, as well as his M.Sc. degree in Nanoelectronic Engineering (with honors). As part of his M.Sc. study (2011) he did his master thesis at imec where he focused on characterization of high-k metal-gate interface using backside XPS and electrical scanning probe microscopy. He is pursuing a Ph.D. degree at the KU Leuven performing his research at imec on metrology and physical mechanisms of emerging memory devices. His Ph.D. is supported by a grant from IWT. Umberto’s research aims to overcome traditional limitation of electrical scanning probe techniques by developing concepts to transition from 2D-observation toward the 3D characterization of nano-sized volumes. He recently obtained the IEDM 2013 Roger A. Haken Best Student Paper Award for his work ‘Conductive-AFM tomography for 3D filament observation in resistive switching devices’.
GaN HEMTs for Millimeter-Wavelength PowerAmplifiers
As GaN-based amplifier technology is garnering interest due to its inclusion into major proposed DoD systems, we look to extend the operating frequency and scale the output power of the technology to the millimeter-wavelength (MMW) regime (30 – 300 GHz). Enabling power performance in this frequency range not only entails geometric device scaling, but also requires novel heterostructure and device design to facilitate simultaneous high frequency response and high operating voltage. In this regard, it cannot be assumed that the reliability of previous frequency nodes will extend into theMMW regime. In this talk, an overview of the challenges and tradeoffs of scaling GaN-based devices will be presented as well as a look into NRL’s approach to MMW GaN HEMT designincluding initial reliability data at 40 GHz.
Brian Downey earned his B.S. degree in Engineering Science and Mechanics from the Pennsylvania State University in 2006. He continued on at Penn State where he received his Ph.D. in Materials Science and Engineering in 2011. His Ph.D. research focused on the reliability of ohmic contacts to SiC for high current density applications. In 2011, he joined the US Naval Research Laboratory (NRL), where his research is primarily focused on the development of GaN high-electron-mobility transistors (HEMTs). He is particularly interested in extending the power, frequency, and reliability performance of GaN HEMTs into the millimeter-wavelength regime through understanding the effects of materials selection, device design, and device processing on device performance and reliability. Additionally, Dr. Downey assists in failure analysis of GaN technology with the GaN reliability testing laboratory at NRL.
BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs
Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. The traditional 10 year device operation cannot be guaranteed anymore, mainly due to severe Bias Temperature Instability (BTI) of ultra-thin dielectrics. Meanwhile, the introduction of high-mobility channel materials is emerging as the frontrunner option to maintain the usual pace of performance enhancement in next CMOS technology nodes. We present a review of our recent studies of BTI in different material systems, highlighting the reliability opportunities and challenges of each device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge pMOS technologies if a Si cap is used to passivate the channel and to fabricate a standard SiO2/HfO2 gate stack. We ascribe this superior reliability to a reduced interaction of channel holes with oxide defects, thanks to a favorable energy alignment of the (Si)Ge Fermi level to the dielectric stack. We discuss gate stack optimization (Ge fraction, quantum well and Si cap thicknesses, channel strain) for maximum BTI reliability, and we propose a simple model able to reproduce all the experimental trends. We then use the model to understand the enhanced BTI in different high-mobility channel gate stacks as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability.
Jacopo Franco received the B.Sc. and M.Sc. in Electronic Engineering cum laude from Università della Calabria - Italy, in 2005 and 2008 respectively, and the Ph.D. degree in Engineering summa cum laude from KU Leuven - Belgium, in Jan. 2013. He is currently a Researcher in the CMOS FEOL reliability group of imec - Belgium. His research interests focus on the reliability of high-mobility channel transistors for future CMOS nodes, and on variability issues in nanoscale devices. He has authored or co-authored 80+ papers in international journals and conference proceedings, one patent, one book and several book chapters. He is a recipient of the Best Student Paper Award at SISC (2009), the EDS Ph.D. Student Fellowship (2012), the EDS Paul Rappaport Award (2011), and the Best Paper Award at IRPS (2012).
Defects in MoS2 and other TMDs: Impact on Device Performance and Variability
Understanding and controlling point defects and impurities is vital for the realization of nanoelectronic devices based on transition metal dichalcogenides. We find that intrinsic defects in MoS2 dominate the metal/MoS2 contact resistance and provide a low Schottky barrier independent of metal contact workfunction. Furthermore, we show that MoS2 can exhibit both n-type and p-type conduction at different points on a same sample. We identify these regions independently by complementary characterization techniques and show how the Fermi level can shift by 1 eV over tens of nanometers in spatial resolution. We find that these variations in doping are defect chemistry related. We will discuss how to passivate these defects and show our promising recent results of epitaxially grown TMDs for large area device applications.
Christopher Hinkle is an Assistant Professor of Materials Science and Engineering at the University of Texas at Dallas (UT-Dallas), joining the faculty in the fall of 2009. He received his Ph.D. degree in 2005 in physics from North Carolina State University. Dr. Hinkle's expertise focuses on the growth, characterization, and device physics of semiconductor materials and interfaces for use in a wide variety of devices. He is particularly interested in the heterogeneous integration of III-V, III-N, and two-dimensional materials for applications related to advanced CMOS and power devices, energy harvesting, and energy storage. He has authored or co-authored over 70 publications in peer-reviewed journals and presented more than 40 contributed and 20 invited talks at international meetings. He is a member numerous professional organizations including APS, AVS, ECS, IEEE, and MRS.
Fundamental Material Aspects of Thermal-Mechanical-Electrical Reliability of Low-k Dielectric Materials and Cu Interconnects
Due to significantly reduced material properties relative to SiO2, low-k dielectric materials present considerable thermal, mechanical, and electrical reliability concerns when integrated as the interlayer dielectric in Cu interconnect structures. The complex chemical structure and presence of nano-porosity in low-k materials also present significant challenges in the fabrication and characterization of nano-patterned metal interconnects. In this address, these challenges and their origin will be briefly reviewed and recent progress in understanding the structure-property relationships in low-k dielectric materials will be presented along with new advances in materials metrologies that enable the characterization and failure analysis of low-k materials and Cu interconnects at the nanometer scale. Specific topics likely to be covered will include: photoelectron and electron energy loss spectroscopy measurements to map the band alignment (i.e. “band diagram) and presence of defect states in low-k/Cu interconnects, nano-scale AFM based FTIR measurements to elucidate the chemical structure of nano-patterned low-k materials; and optical and AFM based measurements to deduce the mechanical properties of nanometer scale thin films and metal interconnect structures. It will be demonstrated that these techniques, when combined with constraint and bond rigidity percolations theories, can enable a greater understanding of the structure-property relationships in low-k materials that should enable a more rational design of future ultra low-k materials for metal interconnects with improved reliability.
Dr. Sean King is a Senior Technical Contributor and Process Development Engineer in Intel’s Portland Technology Development (PTD) Division. Dr. King received a B.S. degree in Materials Engineering from Virginia Tech in 1991, and a Ph.D. in Materials Science and Engineering from North Carolina State University in 1997. Since joining Intel in 1997, Dr. King has held a variety of technical positions in the development of Intel’s 0.35 µm and 130-10 nm technologies. In 2004, he received Intel’s highest achievement award for the insertion of low-k dielectrics in the 90 nm technology. Currently, Dr. King is leading the development and integration of low-k dielectric films for use in Intel’s 10 and 7 nm Cu interconnect structures. Dr. King has authored or co-authored over 100 publications in the fields of dielectric and semiconducting materials and holds 25 patents. In addition to low-k materials and interconnect technologies, Dr. King’s current research interests include thin film deposition and epitaxy, diffusion barriers, surface analysis, plasma processing, and the chemical, electrical, and mechanical properties of material interfaces. Dr. King is member of the American Physical Society, American Vacuum Society, Materials Research Society, and The Electrochemical Society.
High Reliability/Supply Chain Risks
Reliability issues associated with the Hubble Space Telescope and current supply chain risks provide a snapshot into the challenges the government currently faces. As the open literature provides more insight into the techniques of creating functional devices with undetectable defects, reliability evaluations provide insight into this threat space. The demand for cheaper electronics continues to grow and validation for these devices is being minimized due to resource limitations within the government. There are technologies available to solve some of the supply chain problems but each has its own limitations. The presentation will provide an overview of the security complexity and emerging issues in semiconductor hardware which look to leverage the exciting work this community provides.
Daniel M. Marrujo
Daniel Marrujo is the Lead Microelectronics Reliability Engineer at the Defense Microelectronics Activity.
Daniel Marrujo, a native of Sacramento, Ca., began his career in 2008 at Raytheon Missile Systems in Tucson, AZ., developing missile guidance systems for their advanced programs. Mr. Marrujo moved to the Defense Microelectronics Activity (DMEA), Sacramento, CA., in 2009 working for the Trusted IC program office. In 2010 he began working towards development of DMEA’s reliability capabilities and was selected as part of the leadership team for the National High Reliability Electronics Virtual Center. Daniel has provided his technical expertise on multiple DARPA programs as a subject matter expert. He has also provided his support to NASA related efforts. His research is focused on supply chain risk management, CMOS reliability, reverse engineering and radiation effects.
Daniel holds a Masters Degree in Materials Engineering and a Bachelors Degree in Electrical Engineering from the California Polytechnic State University, San Luis Obispo, CA.
Re-investigation of Hydrogen-Related Defect Generation in Gate Dielectric Interface and Bulk
Issues concerning the reliability of ultra-thin gate dielectrics constitute one of the most serious challenges in the scaling of ULSI devices. In order to realize highly reliable gate dielectrics, the elimination of defect generation at the interface and in the bulk are indispensable. However, the origin of the defects and their generation processes are still controversial. One of the generally accepted models is that hydrogen, which is released from the interface during electrical stressing, strongly relates to the deterioration of the gate dielectrics. For example, the hydrogen release processes in NBTI, CHC, and TDDB are well-known. In this study, we re-investigate and discuss the relationship between hydrogen and defect generation in both the interface and bulk of typical SiO2 systems from both experimental and calculation points of view. And, we further discuss the hydrogen-related degradation in High-k gate dielectrics.
Yuichiro Mitani received the B. E. and M. E. in material science and engineering from Tohoku University, Sendai, Japan, in 1990 and 1992, respectively. He received the Ph.D. from the University of Tokyo in 2009. He joined the R&D Center, Toshiba Corporation in 1992. His research interests include characterization and process engineering of CMOS and Flash memory devices, and device reliability. He has published more than 20 papers (more than 50 papers including co-authored) in peer-reviewed journals and conference proceedings and acted as a reviewer of several international journals. He served on the technical committees of the IEEE International Conference on IC Design & Technology (IEEE ICICDT) since 2005 (He served as a session chair of the Process-induced damage / Reliability session since 2009) and the IEEE International Reliability Physics Symposium (IEEE IRPS) since 2005. He served as a chair of the Gate Dielectric (GD) Session at IRPS in 2011. He also served as a CRY technical committee member of the IEEE International Electron Device Meeting (IEEE IEDM) since 2013.
Impact Factors for BTI Lifetime Prediction
Today Bias Temperature Instability is the most prominent device degradation mechanism of MOSFETs. A big part of currently published reliability papers deal with BTI. The detailed degradation mechanism behind is still under discussion. Exploration is on-going.
However, for lifetime predictions for transistors or complete products, the daily work of reliability engineers of semiconductor companies, it is only secondarily if reaction/diffusion or switching traps are the correct microscopic mechanism. A lot of other aspects play important roles for accurate BTI lifetime extrapolations. Detailed requirement profiles, proper test-structures, accurate measurement techniques, correct consideration of recovery, and a deep understanding of circuit functions and more are impact factors for a safe and accurate reliability assurance. My talk will address these issues for BTI lifetime predictions. It will discuss both, hazards like adulterant influences of measurement delay or PID of test-structures as well opportunities like the s-curve behavior of AC-stress. Finally, some simple guidelines are set up.
Dr. Christian Schlünder has received his Dipl.-Ing. (1999) in electrical engineering and his doctoral degree in engineering science (2006) accompanying his regular work (both from the Technical University of Dortmund, Germany).1999 he joined Infineon as a member of the Corporate Research Department. In the year 2000 he changed to the Corporate Reliability Methodology Group. Today, as a Senior Staff Engineer, he manages technology qualification and quality assurance for various state-of-the-art CMOS & Smart-Power-Technologies.Christian Schlünder authors / co-authors more than 45 papers in various conference proceedings and microelectronic journals. Furthermore he has written a book chapter on Hot Carrier Stress in different circuit applications. Additionally, he has presented invited talks and tutorials at many conferences such as ‘IRPS’, ‘ESSDERC’, ‘DATE’ or “ZuE”. He is frequently a member of the Technical Program Committee of the IEEE-conferences ‘IRPS’ and referee for several microelectronic journals.
Read Current Variability and Random Telegraph Noise (RTN) in Scaled Resistive Random Access Memory (RRAM) devices
RRAM devices utilizing a filamentary conduction mechanism have attracted significant attention due to their unique scalability, excellent switching speed, and endurance. On the other hand, the RTN– like read current instability and cycle-to-cycle variability observed in these devices are still a concern from operational standpoint.
In this study, we investigate the impact of switching conditions on HRS/LRS read instability/noise and variability by employing a fully automated measurement setup, which is capable of effectively collecting low resistive state (LRS) and high resistive state (HRS) read current values during the cycling under different AC SET/RESET conditions,. Analysis of the read current variation over a statistically significant number of switching cycles allows extracting the parameters of the distributions of variability and reading instability amplitudes in both HRS and LRS. We discuss physical mechanisms for the LRS and HRS instability explaining how it is impacted by scaling of the operating current.
Dr. Dmitry Veksler is a Member of Technical Staff at SEMATECH. He received Ph.D. in Physics degree in 2007 from Rensselaer Polytechnic Institute in Troy, NY. His dissertation was devoted to THz plasmonics, and plasma-wave electronic devices for THz spectroscopy and imaging applications. In 2009 he joined Electrical and Physical Characterization group at SEMATECH. His current research focus is on nanostructured materials and devices modeling/characterization/ reliability, and electrical defect metrology. He is particularly interested in non-volatile memories, based on transition metal oxides, and in 2D material devices (for beyond CMOS applications). Also he is interested in Biosensors, Neural networks, and Solar cells research. He has authored and co-authored over 90 technical publications in journals and conference proceedings.