Fallen Leaf Lake

Tutorial Program

The 2014 workshop list of tutorials is as follows:



Hsueh-Rong Chang

International Rectifier

Reliable IGBTs for Hybrid/Electrical Vehicles (H)EV

In recent years, the automotive industry has brought stringent reliability constraints on power electronic systems with focus on cost-effective solutions. The high voltage and high current required in hybrid electric vehicles (HEVs) and electric vehicles (EVs) present technical challenges for power conversion beyond those normally associated with vehicle electrical and electronic systems. An increasing demand for fuel and energy efficiency warrants light weight and small volume power control unit (PCU) in (H)EV applications. Insulated Gate Bipolar Transistor (IGBT) is the power device of choice for the power control unit (PCU) which typically consists of one to two inverters plus a boost converter. The inverters require relatively low switching frequency (up to 20 kHz) and high current while the boost converter warrants high switching frequency up to 170 kHz and relatively low current. Cost reduction in the IGBT modules is the key factor to make (H)EV cars affordable. IGBTs are of paramount importance for the reliability of (H)EV power train due to their high internal electric fields and subject to large junction temperature swings during normal operation. In this tutorial, we review the design, fabrication, and package of reliable IGBTs for automotive industry and discuss the strategies to further improve its reliability.

Since 2005, Hsueh-Rong Chang has been leading her team on the design and product development of advanced IGBT and diode platforms at International Rectifier. The new COOLIRTM silicon platform excel and differentiate IR in performance, ruggedness and advanced feature-sets which brought IR into a technology leader position in the automotive HV power management segment. She also led the research efforts in developing SiC power switches and modules at Rockwell Scientific and demonstrated the world’s 1st SiC-based motor drive and high voltage DC-DC converter with 35-65% size reduction. Hsueh-Rong was awarded Rockwell Technologist of the year 2002. Prior to joining Rockwell Scientific in 1997, Hsueh-Rong invented, developed and demonstrated the 1st trench IGBTs at General Electric, yielding superior performance and worldwide recognition. She received her Sc.D. in Chemical Engineering from Massachusetts Institute of Technology in 1981. She served as technical program committee of ISPSD from 2004 to 2013. She holds 30 US patents and authored/co-authored more than 60 papers.

Laura Frisk

Tampere Univ.

Use of polymer and plastic materials in electronics applications from the reliability point of view

Polymer and plastic materials are used increasingly in electronics applications. Not only are they used as insulating materials, but they are also widely used as structural components, protective materials, and even as electrically conductive materials. Polymers have many considerable advantages compared to metals and ceramics. These include for example lightness, low cost, ease of manufacturing, and high versatility. New polymer materials have been developed for many applications and this has further increased their use in electronics for example as structural parts. Furthermore, polymers are commonly used as a part of composite materials which enables their use in new applications such as electrically conductive materials. From the reliability point of view polymers may be problematic as they are typically less stable than the ceramic and metal materials they are used to replace. Most polymers have poor thermal properties, which needs to be taken into account when they are used. Additionally, humidity and other environmental conditions may markedly decrease the mechanical and electrical properties of these materials. Accelerated life testing (ALT) is commonly used to assess the reliability of various structures and materials used in electronics. This is important especially when new structures and materials are designed. When metals and ceramics are replaced with polymers, environmental test conditions may need to be considered again, as the standard test conditions or previously used test conditions may not be meaningful anymore. Consequently, careful consideration of accelerated test conditions is needed with polymer materials to ensure that they accelerate correct failure mechanisms.

In this tutorial the properties of polymer materials are discussed considering their effect on the long term reliability of a product. Several examples from different electronics applications are discussed. These include protective materials used in electronics, electrically conductive adhesives (ECA) and their use in interconnections, radio frequency identification (RFID) tag materials, and printed circuit board (PCB) materials. Additionally, the results of several different commonly used thermal cycling and shock tests conducted for various electronics products having polymer structures are presented and the test methods are compared and analysed. Additionally, comparison of different constant humidity and humidity cycling tests are presented.

Laura Frisk received her M.Sc. degree in materials sciences and her Ph.D. degree in electronics from Tampere University of Technology (TUT), Finland, in 2000 and 2007 respectively. In 2013 she was granted an adjunct professorship (TUT) in the field of reliability issues in electrical engineering. Currently, she works in TUT, Department of Electrical Engineering, where she is in charge of the research of the Reliability Research Group. In 2013 she started as EU Marie Curie Visiting Research Fellow in Imperial College London (ICL), UK. The aim of her research in ICL is to study the reliability of organic semiconductors and test methods for these materials. In addition to organic semiconductors, her current research interests include electronics packaging and interconnections, materials in electrical engineering, reliability testing and failure analysis. For several years she has studied electrically conductive adhesives and lead-free solders, especially their use in harsh conditions and factors affecting the reliability of the joints. She has studied materials used in electronics packaging and in protection, including, for example, various printed circuit board materials and protective materials. She has also studied reliability testing methods and the development of new test methods by combining several different test conditions during testing. Her work in the Reliability Research Group is conducted in close collaboration with many international industrial partners and the group has several industrial projects running in the area of electronics packaging, materials and reliability. Laura Frisk has authored over 70 papers in peer-reviewed scientific journals and conference proceedings.


Ken Lee


Bit Error Rate Engineering for Spin-Transfer-Torque MRAM

Probabilistic nature of magnetic tunnel junctions (MTJs) poses a new type reliability challenges for spin-transfer-torque MRAM (STT-MRAM). Switching current and thermal barrier need to be co-optimized to control bit error rate margins of STT-MRAM. This requires deeper understanding about thermal disturbance and soft write errors of MTJ devices. In this tutorial, we review basic mechanisms that govern the bit error rates of STT-MRAM and discuss the effect of the probabilistic nature of MTJ devices on STT-MRAM reliability engineering.

Since 2008, Kangho Lee has been working onMRAM device/material engineering, metrology development and cell characterization, andfailure analysis at Qualcomm. He also worked on ultra-low power III-V transistors at Intel, Advanced Transistor and Nanotechnology Group as an intern in 2007. He received his Ph. D. in electrical and computer engineering from Purdue University in 2007. Before starting his Ph. D., he worked on multimedia software/firmware development at a venture company, MbyN Inc., South Korea from 2000 to 2003, following his B.S. from Seoul National University. He was a recipient of Samsung Scholarship. He has 19 US patents granted and has authored more than 25 papers. He is a member of the technical committee, CMOS Emerging Technologies and the program committee of non-volatile memories workshop.


Jean Liao


FEOL Reliability

For modern VLSI, continuous gate oxide thickness scaling poses significant Front-End-of the Line (FEOL) reliability challenges. For instance, Time-Dependent Dielectric Breakdown (TDDB) and Hot-Carrier Injection (HCI) were the most dominant intrinsic FEOL failure mechanisms in traditional CMOS devices. Negative Bias Temperature Instability (NBTI), in additions, had been identified as a significant reliability concern due to dramatic electric field rising in highly scaled technology nodes. To alleviate the rapid gate leakage increases associated with aggressive oxide scaling, High-k dielectric with Metal Gate (HK/MG) has been implemented to replace Si-oxynitride (SiON) with Poly-Si. Besides, new architecture as the three-dimensional FinFET was invented to abate short channel effects. Those evolutions led to new reliability concerns, such as Positive Bias Temperature Instability (PBTI) and Stress-Induced Leakage Current (SILC).

Here the topic includes an overview of key FEOL reliability challenges, status, and the corresponding learning nowadays. To address the physics, several characterizations such as polarity dependence on BTI and SILC in relation to HK/MG devices are discussed. Finally, future challenges and opportunity for FinFET reliability are also introduced.


P.J. Liao received her M.S. degree in Electrophysics from the National Chiao Tung University, Hsinchu, Taiwan, in 1998. She then joined the Technology Quality and Reliability Division at Taiwan Semiconductor Manufacturing Company (TSMC), where her research centered on theory and mechanism of CMOS gate oxide integrity and device reliability. She has been engaged in the process and device development of over five silicon logic technology generations and has published numerous technical papers in semiconductor device and process technology. She is currently working on FEOL reliability pathfinding for TSMC's advanced process technology.



John Suehle

NIST and Image Engineering Inc.

Sunday Night Tutorial: The Magic of Lasers in Entertainment—Behind the Technology

It was not long after the invention of the laser that artists began using this unique source of light in a variety of creative demonstrations, displays and live performances. Beginning in the late 1970s, argon and krypton ion lasers were capable of producing many watts of multi-color visible laser light that could be scanned over a 2-dimensional plane at high speed with mirrors attached to galvanometers. The result was full color vector-drawn laser graphics that could be projected on surfaces as large as skyscrapers or even mountain sides. Even more impressive are volumetric areal beam affects that can be produced as the beam scatters from particulates in the air such as humidity or artificially induced fog. Today, advances in laser technology have enabledtheir use in creative applications that were not previously possible.This presentation will cover the history, technology, and safety issues for large laser light show productions. I will show specific examples from my company, Image Engineering, of how we use high powered lasers in the film industry, professional sports, corporate theater, and with video mapping technology to produce visually stunning displays and productions.

John S. Suehle received his B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Maryland, College Park, in 1980, 1982, and 1988, respectively. Since 1982, he has been working in the Semiconductor Electronics Division at NIST, where he is Leader of the CMOS and Novel Devices Group and has over 30 years of experience in semiconductor device research, specifically in the area of metrology and reliability physics. His research activities include failure and wear-out mechanisms in semiconductor devices, radiation effects in microelectronics, micro-electro-mechanical-systems (MEMS), and metrology issues related to future electronic devices. Dr. Suehle founded Image Engineering Inc. in 1992 with his two brothers. Since then, Image Engineering has become an industry leader in innovative and unique special effects and visual presentation management using the choreography of lasers, video projection, lighting and pyrotechnics.Clients include Walt Disney World, the NFL, major concert acts such as Rihanna, nationally televised shows such as America’s Got Talent, The Country Music Awards, the film industry, and numerous corporations. Dr. Suehle is a Fellow of the IEEE and a member of Eta Kappa Nu.


Lars-Erik Wernersson

Lund Univ.

III-V Nanowire MOSFETs

III-V MOSFETs are currently attracting considerable attention due the advantageous transport properties of the III-V materials. The recent development includes realization of transistors with transconductance values that are comparable or higher than state-of-the-art III-V HEMTs. Low on-resistance has further been achieved by the use of epitaxial regrowth technologies. However, to maintain electrostatic integrity as the gate length is scaled, the transistor evolution suggests the introduction of non-planar geometries, following the development of the Si technology. In this talk, we will review the current status of the III-V MOSFET evolution with a special emphasis on the III-V nanowire MOSFETs fabricated in lateral or vertical geometry. Strategies to reduce the off-state leakage current and to improve the breakdown characteristics via heterostructure design will be presented. We will also show first examples on strategies for the co-integration of all-III-V n- and p-type devices.

Lars-Erik Wernersson received the M.S degree the Ph.D. degree in Solid State Physics at Lund University in 1993 and 1998, respectively. Since 2005 he is Professor in Nanoelectronics at Lund University, following a position at University of Notre Dame 2002/2003. Since 2008 he is Head of Circuits and Systems at the Department of Electrical and Information Technology. His main research topics include nanowire- and tunneling- based nanoelectronic devices and circuits for low-power electronics and wireless communication. He has authored/co-authored more than 150 scientific papers. He has been awarded two individual career grants and he serves as Editor for IEEE Transaction on Nanotechnology.

Ehrenfried Zschech

Institute for Ceramic Technologies and Systems, Dresden, Germany

Managing Stress-Induced Effects on Performance and Reliability of 3D IC Stacks

The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction) and finally on device performance degradation are challenges in advanced 3D integration technologies and product development . Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV stacking technology. It requires the determination of a set of accurate materials data, for wafer-level and package-level structures, needed to feed a materials database that comprises the input parameters for simulation. Particularly the generation of materials data such as (local and effective) Young’s modulus, Poisson ratio and (effective) coefficients of thermal expansion (CTE) on several scales will be described. Particularly for sub-mm structures, materials properties change depending on the size of the structure. For some materials, especially the materials used in packaging, these characteristics are a non-linear function of temperature, i. e. temperature-dependent materials data have to be determined. For polycrystalline materials, their microstructure has to be considered.Eventually, local stress measurements are needed for model validation and calibration, to determine the effect of the TSV/package-induced stress on the transistor performance and reliability. Due to the high resolution needed, the only direct technique to measure strain in transistor channels is TEM.



EhrenfriedZschech is Division Director for Materials and Nanoanalysis at Fraunhofer Institute for Ceramic Technologies and Systems in Dresden, which he joined in 2009. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. EhrenfriedZschech gathered experience in industry, during 17 years in several technical and management positions at Airbus and AMD. He has published three books and more than 170 papers in scientific journals in the areas of solid-state physics, materials science and reliability engineering. He holds honorary professorships for Nanomaterials at the Brandenburg University of Technology in Cottbus-Senftenberg and for Nanoanalysis at the Dresden University of Technology. EhrenfriedZschech is acting as Past President of the Federation of European Materials Societies (FEMS).