John Conley, Jr.
Engineering the Performance of MIM Tunnel Diodes and Capacitors with ALD Nanolaminate Bilayer Insulators
Thin film metal-insulator-metal (MIM) devices find application not only as back-end-of-line (BEOL) capacitors (MIMCAPs), but also as tunnel diodes for optical rectenna based IR energy harvesting, IR detectors, large area macroelectronics, hot electron transistors, and as selector devices to avoid sneak leakage in resistive memory (RRAM) crossbar arrays. This invited talk will highlight how nanolaminate combinations of insulators deposited via atomic layer deposition (ALD) can be used to enhance the performance of MIIM diodes and MIIM capacitors as well as discuss reliability issues.
First, the dominant conduction mechanisms, barrier heights, performance, and reliability of MIM diodes fabricated on smooth metal bottom electrodes using a variety of single high and low electron affinity (χ) ALD insulators will be discussed. Next, it will be shown that the performance of dual insulator MIIM diodes may be enhanced through either (i) "step tunneling," a situation in which an electron may tunnel through the smaller χ insulator into the conduction band of the larger χ insulator, or (ii) "defect enhanced direct tunneling," (DEDT) in which electrons injected from the electrode adjacent to the larger χ layer transport easily across this insulator via defect enhanced (DE) Frenkel-Poole emission before direct tunneling (DT) through the smaller χ insulator. In both ST and DEDT, electrons emitted from the opposing electrode under the same magnitude bias of opposite polarity must tunnel through both insulators. The difference in tunneling path between the two polarities results in increased asymmetry and can overwhelm the influence of dissimilar electrodes.
For scaled MIMCAPs, low leakage, high capacitance, and low voltage nonlinearity are desired. Voltage nonlinearity is characterized by the quadratic coefficient of capacitance (αVCC) and typically increases with power law dependence on the inverse thickness of the insulator. The use of bilayer insulators with complimentary properties allow for a reduction of the quadratic coefficient of voltage non-linearity through the cancelling effect while still retaining high capacitance, low leakage, and long lifetime, effectively meeting ITRS 2020 requirements.
Overall, nanolaminate insulators are shown to be an effective way to engineer MIM device performance.
John F. Conley, Jr. received the B.S. in Electrical Engineering (1991) and Ph.D. in Engineering Science and Mechanics (1995) from The Pennsylvania State University where he won a Xerox award. He has been a senior member of the technical staff at Dynamics Research Corporation and the Jet Propulsion Laboratory, the Leader of the Novel Materials and Devices Group at Sharp Laboratories of America (SLA), and an adjunct professor at Washington State University-Vancouver. Since 2007, he is a Full Professor of both Electrical Engineering and Computer Science and of Materials Science at Oregon State University where he is also an ONAMI Faculty Fellow and co-Director of the Materials Synthesis and Characterization (MASC) facility. He has served multiple times as guest editor for IEEE Transactions on Device and Material Reliability, on the committees of the IEEE IRPS, SOI, and NSREC, the MRS EMC, the AVS meeting, and upcoming 2015 ALD conference, and as technical program chair of the IEEE IIRW and the IEEE MRQW. Dr. Conley's current research interests include atomic layer deposition (ALD), metal/insulator/metal devices (MIM & MIIM tunnel diodes, MIM high-κ capacitors, and RRAM), internal photoemission (IPE), thin film transistors, nanomaterials, sensors, and electron spin resonance (ESR) identification of electrically active point defects in novel materials. Dr. Conley has authored or co-authored over 120 technical papers, over 130 additional conference presentations (including tutorial short courses on high-k dielectrics and more than 15 invited talks), and twenty U.S. patents, which together have received more than 2,900 citations (Google Scholar). Dr. Conley is a fellow of the IEEE.
Reliability challenges in resistive switching memories technology
There has been an increase in the demand for flash memories due to tremendous increase in sale of hand-held devices like tablets, smart phones, digital cameras etc. However, further scaling of NAND flash memories have shown profound limitations due to significantly degraded performance and reliability. Metal oxide based resistive switching memories (RRAM) are receiving considerable interest as an alternative non-volatile memory application due to its high scalability. A typical RRAM device can be switched between high and low resistance states stability (HRS and LRS), respectively state by RESET and SET operations. One of the potential concerns for manufacturability of RRAM devices is the cycle to cycle variability of the HRS and LRS. In this talk, I will first cover the trade-off between various HfOx RRAM performance parameters like low resistance state (LRS), high resistance state (HRS), operating voltages and currents as well as speed which are required to demonstrate its feasibility as NAND flash replacement. Secondly, I will discuss the statistical methodology for assessing the variability in HfOx based RRAM devices. It will cover the impact of switching speed and number of endurance cycles on the cycle to cycle variability in these devices.
Dr. Shweta Deora obtained her PhD in electrical engineering from Indian Institute of Technology Bombay in 2011. From 2005 to 2006 she was working as research assistant on the radiation sensor development project with IIT-Bombay. Since July 2011, she has been with SEMATECH, Albany, NY, working as device engineer in Process technology (PT) group working on various resistive random-access memory systems, high mobility channel MOSFET devices as well as semiconductor clean technologies. Her research focuses on test structure development, process optimization, electrical characterization, modeling and reliability for advanced logic and memory devices including III-V, SiGe, Ge, 2D-TMD, RRAM with various oxides and MTJ as well as semiconductor surface clean modeling. She has served on the technical committee of the IEEE International Reliability Physics Symposium (IRPS) in 2014 and 2015.
Defect Limited Reliability and Transport in Carbon Nanotube and Graphene Devices
A recent report by the U.S. Energy Information Agency indicates that global energy consumption has increased by approximately 40% over the past 15 years, due in large part to advances in information technology and increased energy demand in residential and commercial buildings. Tackling such a looming challenges is going to require innovation and scientific discovery. Nanotechnology will be an important aspect of this process. In particular, carbon nanomaterials (e.g. 1-dimensional carbon nanotubes and 2-dimensional graphene) show great potential for the development of energy efficient nanoelectronics and thermal management materials. This is attributed to their inherent low-dimensions, high carrier mobility, and large thermal conductivity. The ability to tune these intrinsic properties by introducing defects or engineering external influences creates interesting fundamental challenges and new opportunities. In this talk I will discuss the role of such defects on reliability, power dissipation, and thermal transport in carbon nanotube and graphene based devices and films.
David Estrada is an Assistant Professor of Materials Science and Engineering at Boise State University (BSU). From 1998 to 2004 he served in the United States Navy as an Electronics Warfare Technician/ Cryptologic Technician - Technical. He received his Bachelor of Science in Electrical Engineering from BSU in May of 2007, after which he joined Professor Eric Pop’s group at the University of Illinois at Urbana-Champaign (UIUC). David received his Master of Science in Electrical Engineering from UIUC in 2009, and his Doctor of Philosophy in Electrical Engineering at UIUC in 2013. He is the recipient of the NSF, NDSEG, SURGE, and Micron Graduate Fellowships. His work has been recognized with several awards, including the Gregory Stillman and John Bardeen graduate research awards. Most recently, he was awarded a summer fellowship with the United States Air Force to work on printing emerging nanomaterials for device applications. His research interests are in the areas of printed and flexible electronics and bionanotechnology.
A sampling approach for efficient BEOL TDDB assessment
As semiconductor manufacturing process becomes more and more complicated in advanced technologies, time-to-fail characteristics of BEOL TDDB are often significantly affected by within-wafer process variations, especially in early development stages. With the presence of such an effect, an accurate estimation of TDDB model parameters becomes difficult and sometimes erroneous values can be observed, which may lead to an erroneous conclusion. In order to minimize an artifact of process variation effect on the model parameters, we propose and demonstrate a practical approach of ramped-voltage sample screening followed by, based on voltage screening, grouping of unstressed samples for TDDB stresses, determination of voltage stress sequence on samples, and use of dynamically generated stress wafermap instead of using a predetermined checkerboard pattern wafermap. It is also demonstrated that the proposed approach can help greatly improve the accuracy of long-term TDDB stress results, without invoking large sample studies. An example will be given with this sampling approach how a voltage acceleration parameter can be affected depending on the choice of samples.
Dr. Andrew Kim is currently a senior reliability engineer at Technology Quality and Reliability of Server Group, IBM Systems, Hopewell Junction, NY, involving in 14nm, 10nm and 7nm BEOL Technology Reliability. He received his Ph.D. (2001) in mechanical engineering from Rensselaer Polytechnic Institute, Troy, NY. Starting with a professional career of designing GE's 7H steam-cooled gas turbine stage-1 bucket at GE Power Systems (1998-2000, Schenectady, NY), he joined TCAD group of Texas Instruments, Dallas, TX in 2002, upon receiving Ph.D. on the modeling of chemical mechanical planarization (CMP) process (Elastohydrodynamic Contact Model), where his focus was on the research/development of strained silicon processes for planar devices, CMP and BEOL EM/SM reliability. From 2004 to 2010, he was a manager and a technical leader of BEOL reliability team of LSI Business Division of Samsung Electronics Co. Ltd., South Korea. Dr. Kim was a senior systems reliability consultant for heavy duty industrial gas turbines business at GE Energy (2010), Schenectady, NY, and a senior member of technical staff at GlobalFoundries (2011-2012), Hopewell Junction, NY, working on 20nm BEOL process integration, prior to joining IBM in 2012.
Reliability Aging and Modeling of Chip Package Interaction on Logic Technologies Featuring High-k Metal Gate Planar and FinFET Transistors
Transistor performance and reliability are usually affected by chip-package interaction (CPI) stress. 4-point bending experiments combining finite-element modeling (FEM) and TCAD simulation are conducted to investigate stress evolution from package level to device level. We demonstrate the impact of CPI stress on transistors performance featuring HK/MG planar and FinFETs, as well as device aging including PBTI, NBTI, and HCI. FinFETs show larger tolerance regarding stress-induced carrier mobility shifts, which could be comprehensively interpreted by FEM framework. Moreover, in terms of mechanical bending, both planar and FinFETs show comparable device reliability immunity to CPI stress. Typical CPI stress-induced mobility shifts can reach more than 10%, depending on the type, size and location of the device and the structure of the package. Management of carrier mobility shifts and transistor aging by optimized chip package technology are also demonstrated in this study.
Jen-Hao Lee received his B.S. (2001) and Ph.D. (2006) in material science and engineering from National Chiao-Tung Univ., Hsinchu, Taiwan, ROC. He joined TSMC (Taiwan Semiconductor Manufacturing Company) since 2007 and engaged in transistor reliability. His research interests are in the area of NBTI/PBTI/HCI physical mechanism and modeling among oxynitride and high-κ/metal gate technologies, as well as the advanced FinFET devices. Dr. Lee has served as Technical Committee Members in International Reliability Physics Symposium (2013 and 2015), and he also serves as reviews for IEEE electron device society, including Transaction on Electron Devices, Electron Device Letters, and Transactions on Device and Materials Reliability. He is currently working on reliability research for TSMC’s advanced process technologies.
Solid-State-Drive (SSD) Qualification and Reliability Strategy
As NAND flash memories have scaled the margin between NAND capability and system requirements has been significantly reduced. Understanding Solid-State-Disk (SSD) reliability and qualification requirements has become more critical since these impact the NAND flash design tradeoffs. Unrealistically high expectations result in excessive margin that could have been used in other areas, while too low of a requirement puts the system at risk for excessive field failure. The reliability and qualification requirements for SSDs will be reviewed and discussed in order to give an overview of what constitutes an effective qualification/reliability strategy for SSDs.
Todd Marquart is a Fellow at Micron Technology and currently manages the SSD QRA group where he is responsible for the reliability and quality of all Micron SSD products. Previously he worked on the reliability of Micron NAND flash as part of the process R&D group, starting with Micron’s first NAND product. He has been working in reliability engineering for 19 years, the last 11 years with Micron. He received his Ph.D. in inorganic chemistry from the University of Illinois, Urbana-Champaign with post graduate research at Sandia National Laboratories. He teaches semiconductor reliability and life-data-analysis at Micron and has been doing side research with Wes Fulton and Dr. Bob Abernethy on Weibull/life-data analysis.
From WLR to Product Reliability and Qualifications in the 3D Transistor Era
Reliability mechanisms associated with HK+MG transistors including latest FinFETs on 14nm technology node will be discussed along with circuit and product implications on reliabilty stresses and qualifications. Reliability efforts made at the transistor module level to circuit, IP blocks, and finally to a product level reliability will be discussed and limiting mechanisms and examples will be highlighted. As part of the product qual strategy, high-speed HTOL and Set level tests were leveraged to signficantly lower product dpms and seamless introduction of high volume manufacturing.
Dr. Sangwoo Pae, is currently a Director and Group Leader of Technology Q&R group in System LSI Business of Samsung Electronics Co. Ltd. responsible for process and product qualifications. Prior to joining Samsung in late 2012, Dr. Pae was a Q&R program manager at Intel (Hillsboro, OR). During his span at Intel (1999-2012), he has contributed to the development and reliability of Intel’s many logic & SOC process technology nodes and had won many awards including IAAs. He has authored and co-authored over 50+ publications and 30+ patents received/pending in the semiconductor process, circuits, and transistor reliability. He is currently IEEE senior member and has served as technical committee and session chairs at premier IEEE conferences; IEDM (2009-2010) and IRPS (2009-2015) as well giving invited talks. Dr. Pae received his masters (1996) and doctorate degrees (1999) both in Electrical & Computer Engineering from the Purdue University, Indiana, USA.
Aging Model Challenges in Tri-gate Technologies
As trigate transistor technologies continue to scale to smaller dimensions, a variety of aging mechanisms become important to include in models to accurately predict end-of-life transistor performance. Traditional aging effects such as BTI and hot carrier continue to play a role. However, modeling these mechanisms becomes more complicated with the addition of recovery, variation, local self-heating, and BTI/HC interactions. Further, the role of hot carrier degradation is more pronounced in deeply scaled tri-gate technologies since the three-dimensional fin geometry can exacerbate the hot carrier effect, as well the fact that CPU operating voltages are not decreasing while the transistors shrink. As a result, the self-heating effects are increasing, which contribute to degradation and modulate BTI recovery. Additionally, second-order effects are starting to accumulate, such as hot carrier recovery, minority carrier gate injection, damage localization, and trap interactions between hot carrier and BTI. This presentation highlights the roles and impacts of these various effects and details where aging model development work is still needed.
Steve Ramey manages the front-end reliability group in Intel’s Technology Development Quality and Reliability organization and has helped develop the 90nm through 10nm process technologies. He received his Ph.D. in electrical engineering from Arizona State University, M.S. in electrical engineering from University of Nevada, Las Vegas, and B.S. in Physics from Carnegie Mellon University. He has authored/coauthored more than 40 publications on reliability, device modeling, process development, metrology, and photovoltaic devices.
Oxide defects and their Effect on Reliability of III-V and Ge high K gate stacks
The design of gate stacks for the high mobility III-V and Ge based channels has evolved recently with the use of Al2O3 based diffusion barrier inter-layers below HfO2 layers, and possible nitridation. However, the IMEC group  have recently shown that Al2O3has defect states in the wrong energy range, which can lead to a degradation of reliability. I will show how this result is consistent with our electronic structure calculations, and how this might be remedied by nitridation.
 G Groeseneken et al, IEDM (2014); J Franco et al, IEDM (2013)
John Robertson is Head of Electrical Engineering at Cambridge University, UK. He is an expert of electronic materials, and has worked intensively on high K oxides. He is a Fellow of the Royal Society (UK), and of IEEE, APS and MRS.
Samar K. Saha
Electron Devices Society: Activities and Opportunities
The IEEE Electron Devices Society (EDS) is a volunteer-led and volunteer-driven dynamic Society. The mission of EDS is to promote excellence in the field of electron devices for the benefit of humanity. For over 60 years this mission has been achieved through volunteer involvement and dedication. At EDS, we realize our mission in many ways: conferences, publishing, education, and technical recognition. The EDS provides its members with critical resources, community-building opportunities, and support not available through any other organization or society.
Since the early 1990s, when the International Wafer Level Reliability Workshop transitioned into the International Integrated Reliability Workshop (IIRW), EDS, along with the IEEE Reliability Society, has been a proud cosponsor of the conference. Attend this session to learn how EDS is evolving to meet the changing needs of the community, to discover how members can get more involved in the life and work of the Society, and to share your thoughts, insights, and feedback with EDS’s volunteer leaders and staff.
Samar K. Saha is the President-Elect of the IEEE Electron Devices Society (EDS) and an Adjunct Professor at the EE department of Santa Clara University. He previously worked for National Semiconductor, LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, DSM Solutions, Silterra USA, and SuVolta, and served as a faculty member at Southern Illinois University at Carbondale, Auburn University, University of Nevada at Las Vegas, and the University of Colorado at Colorado Springs. He is a member of the editorial board of the World Journal of Condensed Matter Physics, a Scientific Research Publishing journal. He has authored numerous research papers, one book entitled, Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond, CRC Press, Florida (2015); one book chapter on Technology Computer-Aided Design (TCAD), and holds several US patents.
Dr. Saha has served as the Vice President of EDS Publications; an elected member of the EDS Board of Governors; and the Treasurer, Vice Chair, and Chair of the Santa Clara Valley EDS chapter. He has, also, served as the head guest editor for the IEEE TRANSACTIONS ON ELECTRON DEVICES (T-ED) Special Issues (SIs) on “Advanced Compact Models and 45-nm Modeling Challenges” and “Compact Interconnect Models for Giga Scale Integration,” and as a guest editor for the T-ED SI on “Advanced Modeling of Power Devices and their Applications.”
Defect-centric perspective for combined RTN and BTI time-dependent variability
This paper describes the implications of time-dependent threshold voltage variability, induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), on the yield and performance of advanced technology nodes. Investigation of time dependent variability at the individual trap level, e.g. in production environments, is not always feasible with single device measurement approaches developed in academic literature. Nonetheless nFET and pFET time-dependent variability, in addition to standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group. The statistical distributions encompassing both BTI and RTN variability and their correlations are discussed from a defect-centric perspective.
Pieter Weckx received the B.Sc degree in Electronic Engineering and M.Sc. degree in Nanoscience and –technology from the Katholieke Universiteit Leuven - Belgium, in 2009 and 2011 respectively. Currently he is finalizing a Ph.D. degree in the reliability group of imec and at the Katholieke Universiteit Leuven, on the topic of modeling and simulation of time-dependent variability problems in nanoscaled electronic devices, statistical circuit simulations and stochastic/deterministic clustering of circuit degradation behavior.