The 2015 workshop list of tutorials will be announced soon...
Ionizing Radiation Effects in Electronic Devices with an Emphasis on Non- volatile Memories
Introduction to the topic:
The first part of the tutorial will give an overview on the most relevant issues concerning ionizing radiation effects in advanced components. The evolution of CMOS technology following Moore’s law is making electronic devices increasingly sensitive to external disturbances, among which ionizing radiation. Particles with lower and lower ionizing power are able to corrupt a digital bit of information in state-of-the-art devices. Until some years ago, ionizing radiation was an issue only in very harsh environments, such as space or high-energy physics experiments, but today soft errors are a concern even at sea level, especially for high-reliability applications, due to atmospheric neutrons and alpha-emitting contaminants. When an ionizing particle strikes an electronic component, a plethora of different effects may occur, depending on the type of device and impinging radiation. These effects may be transient, permanent or even destructive. Single event effects, stochastic events that occur when a single particle hits the wrong place at the wrong time, as well as total ionizing dose effects, causing a progressive degradation of the device parameters due to the build-up of charge trapping in oxides and/or interface state generation, will be presented.
In the second part of the tutorial, radiation effects will be discussed in non-volatile memories, in particular floating gate Flash and phase-change memories. NAND Flash memories feature the most aggressively scaled feature size and the largest capacity in the semiconductor market. Phase-change memories (PCM) are one of the most promising technologies to replace NOR Flash. The most recent findings on radiation effects in Flash memories and PCMs will be presented, including technology trends for single event effects, neutron- and alpha-induced soft errors in Flash memories, destructive events occurring in the peripheral circuitry due to single ion strikes, as well as the first ion-induced errors recently observed in phase change memory cells. Total dose effects, relevant for space applications but also for environments with man-made radiation, will be presented as well.
Structure of the tutorial
1. Why should we care about radiation: environments of interest
2. Basic facts about radiation-matter interactions
3. Single event effects
4. Total ionizing dose effects
5. Radiation on Flash memories and PCM: interesting case studies
Who should attend
This tutorial is meant for students, researchers, reliability engineers and physics, working in the fields of aerospace, astrophysics, automotive, medical, high-energy physics, fusion. Anyone who needs to face radiation effects issues will be interested in this tutorial, as well as anyone who is curious about the huge world of radiation effects in electronic devices.
Marta Bagatin received the Laurea degree (cum laude) in Electronic Engineering in 2006, and a Ph.D. in Information Science and Technology in 2010, both from the University of Padova, Italy. She is currently a Post-Doc researcher at the Department of Information Engineering, University of Padova. Her research interests are mainly focused on reliability and radiation effects on electronic devices, especially non-volatile memories. Marta authored or co-authored about 40 papers published in peer-reviewed journals in the field of radiation effects in electronics, about 50 contributions at international conferences, and two book chapters. She regularly serves in the committees of international conferences on radiation effects such as the Nuclear and Space Radiation Effects Conference (NSREC) and RADiation Effects on Components and System (RADECS), and as a reviewer for numerous scientific journals.Biography
Nanoscopic techniques for studying dielectric breakdown and switching induced morphological changes and defects
Introduction to the topic:
Nanoscopic physical analysis of breakdown in high-k gate/metal stacks shows that the microstructural defects and damages induced by dielectric breakdown in high-k gate dielectric are very different from that of conventional SiOxNy/poly-Si gate stacks. Chemical analysis using transmission electron microscopy (TEM) and electrical analysis using scanning tunnelling microscopy provide useful information about the nature and evolution of the breakdown induced defects and the roles of material microstructure responsible for dielectric breakdown in metal-oxide-semiconductor field effect transistors. Together with electrical characterization, various microstructural and morphological changes at nanometer scale to the gate systems have been established. This tutorial will also report the latest TEM study on real-time high-k breakdown induced by an in-situ STM probe in TEM. The effect and role of breakdown induced microstructural changes on dielectric breakdown and recovery (or more commonly called switching) are identified. The impacts of the new breakdown and recovery mechanisms on the performance and reliability of high-k/metal gate stacks are discussed.
Structure of the tutorial
1. Background of ultrathin gate dielectrics breakdown study
2. Experimental details for accurate determination and analysis of breakdown path
3. Physical defects induced by breakdown
4. Chemistry of conductive path in gate dielectrics
5. Breakdown mechanisms in high-k/metal gate stacks by physical analysis
6. Observation of switching behaviors in post-breakdown conduction in NiSi-gated stacks
Who should attend
In this tutorial, an overview of physical analysis techniques like transmission electron microscopy and scanning tunnelling microscopy to study breakdown and switching in ultrathin dielectrics in semiconductor devices will be provided. Many examples and case studies using conventional gate stacks and the advanced high-k gate systems will be presented. The key challenges associated with using these techniques for analytical analysis and its potential for studying the fundamental mechanisms responsible for dielectric breakdown/recovery and switching of future nanodevices will be shared. This tutorial should be of interest to reliability and failure analysis engineers working on gate dielectric reliability and engineers working on resistive switching devices as well as for anyone interested in this topic.
Kin-Leong Pey is currently the Associate Provost of Education and a Professor at the Singapore University of Technology and Design. He was previously Head of the Microelectronics Division, Programme Director of the Si Technology Research group, Director of the Nanyang NanoFabrication Center (N2FC), and the Director of the Microelectronic Centre in the School of Electrical & Electronics Engineering at the Nanyang Technological University, Singapore, and had graduated 30 PhD theses and more than 15 Master theses. Kin-Leong previously held a Fellowship appointment in the Singapore-MIT Alliance and has held various research positions in the Institute of Microelectronics, Chartered Semiconductor Manufacturing, Agilent Technologies and the National University of Singapore.
Kin-Leong has been working on transistor reliability in dielectric breakdown and advanced interconnects for more than 15 years. In particular, Kin-Leong’s group pioneers in using physical analysis techniques in the study of breakdown mechanisms in ultrathin gate dielectric stack. A senior member of IEEE and an IEEE Electron Devices Society Distinguished Lecturer, Kin-Leong has been the organising committee member of IEEE IPFA (Physical and Failure Analysis of Integrated Circuits) since 1995. He was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Hsinchu, Taiwan. Kin Leong is a Fellow of the ASEAN Academy of Engineering & Technology.
Kin-Leong is an Editor of IEEE Transactions on Devices and Materials Reliability. He has published more than 170 international refereed publications, 175 technical papers at international meetings or conferences and a book chapter, and holds 38 US patents.
Yevgeniy S. Puzyrev
Modeling of Hot-carrier Degradation in GaN Transistors
Hot-electron effects play an important role in degradation of GaN high-electron-mobility transistors. The modeling approach presented here includes device simulation and atomic-scale defect description using density function theory (DFT). Hot electrons are generated by high electric fields in semiconductor devices. These energetic electrons can induce or modify defects that affect the device operation. Several degradation mechanisms of GaN-based high-electron mobility transistors (HEMTs) have been described recently in the literature. Experiments show that a variety of defects appear during device operation, but the connection between atomic-scale mechanisms and the degradation rate is difficult to establish. For example, the atomic-scale nature of the traps that produce changes in threshold voltage, leakage current, and drain current is not well known.
Hot-electron effects are believed to play an important role due to the presence of a significant number of electrons with energies above 0.5 eV. The high-energy electrons can transfer large amounts of energy to the lattice and lead to defect generation. We combine electrical measurements, quantum mechanical calculations, Monte-Carlo device simulations and accelerated degradation tests. A relatively simple formulation has been developed under the assumption that the hot-electron scattering cross-section is independent of the electron energy. In this case one can relate the change in defect concentration to the operational characteristics of a device, such as the spatial and energy distribution of electrons (electron temperature), electric field distribution and electron energy loss to the lattice. While the values of electric field and energy can be obtained using device simulators based on Monte-Carlo description of electron transport, the scattering of high-energy electrons at the defects requires quantum mechanical treatment of the scattering cross-section.
In this tutorial we’ll present the steps involved in developing the predictive device reliability protocol. The protocol includes the atomic-scale calculation of defect properties and combines modeling results with the experimental observations of degradation to produce a device degradation rate. The choice of devices and their growth conditions used in validation of the protocol is crucial to understanding the dominant defects and their effect on device operation.
Tutorial is presented in the following sections:
1. Introduction of hot-carrier degradation in GaN.
2. Device simulation of carrier transport.
3. Density functional calculations of defect properties.
4. Defect evolution model and scattering cross-section
5. Integration of carrier transport, defect properties and defect evolution in the degradation model
Who should attend:
This tutorial is on physical mechanism of hot-carrier degradation, including the discussion of current approximations, such as independence of energy for the scattering cross-section of the defects. The tutorial is of interest to reliability engineers working on hot-carrier degradation and related phenomena as well as for anyone interested in this topic.
Yevgeniy Puzyrev received his MSc degree in physics (specialization: optics and spectroscopy) in 2000. He received doctoral degree in physics in 2006 from Florida Atlantic University and then began working as a post-doctoral researcher at Oak Ridge National Laboratory. In 2008 he became post-doctoral researcher and, consequently, research assistant professor at Vanderbilt University. His scientific interests include atomic-scale modelling of hot-carrier degradation in HEMT devices, theoretical investigation of electronic and mechanical properties of two-dimensional as well as memristive materials.
Modeling and Characterization of Hot-Carrier Stress Degradation in Power MOSFETs
Introduction to the topic:
Many applications require devices that are capable of handling voltages well in excess of the low voltage CMOS supply. Both high-voltage (20 to 100 V) and high current (2 to 3 A) output drivers are used within automotive, display drivers, paper media, digital media, and telecommunication applications. In addition, for cost and reliability reasons, there is a continuous trend for integrating power-handling transistors in the low-voltage CMOS process instead of using discrete devices. Hence, the so-called “Smart Power” technologies are now proposed by almost all of the foundries, with platforms incorporating high performance power devices at a wide range of operating voltages. The lateral double-diffused MOS (LDMOS) transistor with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes.
The electrical characteristics of the STI-based LDMOS transistors will be reviewed over an extended range of operating conditions. The high electric-field regime will be explained to the purpose of investigating the effects on the electrical safe operating area (SOA) and device reliability under hot-carrier stress (HCS) conditions. The HCS degradation phenomena in this kind of transistors are strongly related to the specific nature of the device: the current flows laterally and close to the Si/SiO2 interface in all the regions. Hence the degradation probability is expected to be large, and the presence of the thick oxide in the drift region is the main reason for a limited HCS SOA. A review of the HCS physics-based modelling will be addressed to the purpose of understanding the degradation kinetics and mechanisms. TCAD simulations of HCS degradation will be finally shown to explain the HCS effects on a wide range of biases and temperatures.
Structure of the tutorial
1. Introduction to the LDMOS device and its architectural solutions
2. LDMOS reliability: safe operating area and hot-carrier-stress degradation
3. Physics-based modeling of hot-carrier-stress degradation
4. TCAD modeling of hot-carrier-stress degradation
Who should attend
In this tutorial an overview of the lateral power MOS device including the review of the most relevant aspects of the device architecture will be given. Basic electrical characterization of the LDMOS, transport properties in the high-field regime, safe operating area and HCS reliability issues will be discussed. Finally, the modeling issue of the hot-carrier stress degradation will be addressed and different TCAD-based approaches will be presented. This tutorial should be of interest to reliability engineers working on hot-carrier degradation and related phenomena as well as for anyone interested in this topic.
Susanna Reggiani is Associate Professor at the Faculty of Engineering of the University of Bologna, Italy. She received the Ph.D. degree in Electrical Engineering from the University of Bologna in 2001. Since 1997 she is with the Department of Electronics (DEI), University of Bologna, and is currently with the Advanced Research Center for Electronic Systems (ARCES). Her scientific activity has been devoted to the physics, modeling and characterization of electron devices, with special emphasis on transport models in semiconductors. Since 2007 she has been Task Leader of International Projects funded by the American Semiconductor Research Corporation (SRC) in collaboration with Texas Instruments (Dallas, Texas), dealing with the modeling, design and TCAD analysis of low-Rsp power MOSFETs, modeling of hot-carrier stress degradation for TCAD analysis of power MOSFETs, and modeling of package influences on high-voltage semiconductor FETs.
AgELESS: Aging Estimation and Lifetime Enhancement in Silicon Systems
While there has been tremendous progress in understanding reliability mechanisms at the level of individual devices and wires, circuit designers have traditionally used little of this information. By understanding aging mechanisms and percolating aging information to all levels of design abstraction, functional and reliable chips may be built using an aging-aware design methodology that is scalable to the full-chip level. This talk will illustrate techniques used to estimate and enhance the reliability of large digital circuits under the AgELESS project. Practical solutions for analyzing and improving the lifetime of a design, both during the design stage and when the chip is in the field, will be illustrated. At the presilicon design stage, methods at the gate level, circuit level, and architectural level are devised to manage delay degradations due to aging by adding timing margins and by developing strategies that minimize these margins. At the postsilicon stage, surrogate sensors such as ring oscillators are developed, first to predict the performance degradation of an arbitrary circuit block, and then to enhance resilience.
Sachin Sapatnekar received the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1992. He teaches at the University of Minnesota, where he holds the Distinguished McKnight University Professorship and the Henle Professorship in ECE. His research is related to developing CAD techniques for the analysis and optimization of circuit performance, currently focused on CMOS circuits and spintronics. He has served as Editor-in-Chief of the IEEE Transactions on CAD and General Chair for the ACM/IEEE Design Automation Conference (DAC). He is a recipient of several conference Best Paper Awards, the Semiconductor Research Corporation's Technical Excellence Award (2003), and the Semiconductor Industry Association University Research Award (2013), and a Fulbright award (2013). He is a Fellow of the IEEE.
For advanced nodes, semiconductor companies are making a transition to FinFET’s from planar devices. In moving from planar to FinFETs, new features due to 3-d shapes of Fins are introduced. These features can both improve or degrade reliability compared to the planar technologies. This tutorial will first introduce the fundamental concepts and current understanding in basic FEOL Reliability mechanisms such as TDDB, BTI and HCI. It will then provide a review of methodologies used to evaluate these mechanisms. The tutorial will then introduce and review the new features such as corners, sidewalls etc and how they impact FEOL reliability. Additional effects that become more important due to 3-d nature of FinFETs such as self-heating are also discussed and reviewed. The tutorial will attempt to project impact of FinFETs for next generation technologies.
Structure of the tutorial
1. Introduction of FEOL Reliability mechanisms: BTI, HCI, TDDB
2. Current understanding of the physics and projection models
3. Various methodologies to evaluate FEOL reliability mechanisms
4. Introduction of new features in FinFET Reliability
5. Impact and understanding on reliability mechanisms due to 3-d shapes of FinFETs.
6. Future trends of FinFET reliability
Who should attend
This tutorial should be of interest to students and early career engineers as it will cover the fundamentals and current understanding of the FEOL reliability mechanisms. It is also of interest to engineers involved in FinFET development as it highlights challenges and opportunities of FinFET reliability.
Suresh Uppal completed Masters in Science (Hons.) and Master in Technology in Physics in 1997, 1999 in India. He obtained a PhD in Material Science from University of Southampton UK. Following that he has worked on various EU research projects in Si, SiGe CMOS, Gate dielectrics for DRAM application, SiC power devices. He was Globalfoundries assignee at International Semiconductor Development Alliance (ISDA) developing 20nm HKMG technology. His research interests are new methodologies for reliability assessment, understanding the impact of new processes, integration schemes and new features FEOL reliability mechanisms.