Automotive system level reliability dependence on semiconductor capabilities and market dynamics
The qualification of electronic applications (ECU level) or systems (PCB level) as of today is mostly based on a construction check approach which considers the construction principle and interfaces (assembly). Lifetime is generally assumed to be fulfilled when the construction proof is achieved. Unfortunately, available lifetime checks and models of sub-components including semiconductors only proof to 8000 hours to about 15.000 hours for a limited mission profile space. Operation strategies for electrical vehicles like driving, charging, pre-conditioning and on-grid parking result in mission profiles far beyond guaranteed sub-component lifetimes. The truck business and other industries circumvent these challenges with replacement electronics, but corresponding cost ratios are different and critical for cars – at least based on the current supply chain configuration. In parallel, semiconductor technology complexity through scaling, 3D integration and inclusion of more and more new materials within the IC stack rise new uncertainties regarding withstand and lifetime capabilities for automotive, automation, avionics and even the IoT applications - design gaps between original mass volume products and new application fields become more evident. It turns out that these design gaps are not limited to functional aspects and degradation, aging and behavior under severe environmental and operation conditions are virtually Terra Incognita. They have not been investigated due to cost optimization processes regarding focused design targets in the communication and consumer business. Here, we show exemplary results on the effect of secondary (thermo-)mechanical stress that mimics typical automotive load conditions on the functionality of digital blocks as well as on the parameter extraction process for primitive device modelling that is fundamental for any model based verification of IC designs in advanced nodes. Results indicate that lifetime model parameters are altered by these field relevant secondary stresses.
Andreas Aal joint Volkswagen AG, Wolfsburg, Germany, in 2011 with focus on Semiconductor Reliability Assurance (technical development) in Automotive Applications. Now, being responsible on corresponding strategic and operational levels, his activities concentrate on technology capability enhancement of nodes down to 14 nm for automotive applications. He leads two semiconductor related European projects and is a strong representative of the through-the-supply-chain-joint-development approach.
Mr. Aal has been working within the Semiconductor Industry holding different positions from Engineering to Management (Process Engineer, Wafer FAB Project Manager for Process Build-in-Reliability Development, Global Reliability Assurance Manager) working on plasma-damage, failure analysis, production monitoring and process and technology qualification. He was involved in the development of test structure design as well as new combined stress/measurement and data analysis methodologies for qualification and fWLR monitoring on the topics: dielectrics, plasma induced damage and metallization. He accompanied several reliability growth projects and influenced process and technology design for 1.2 um to 0.18 um nodes for both in-house and foundry manufacturing.
Andreas (certified reliability professional) has published and co-authored various papers, has served as reviewer for different Journals and has served in the technical and management committee for IEEE IIRW. He is a member of the IEEE Electron Devices, CPMT, Nuclear and Plasma Sciences, Reliability and Solid-State Circuits Societies and also a frequent participant / contributor of the JEDEC subcommittee 14.2. Since 2007 he is chair of the German ITG group 8.5.6 (VDE) on (f) WLR, reliability simulations and qualification.
SiC Power Device Reliability
SiC power devices offer performance advantages over competing Si-based power devices, due to the wide bandgap and other key materials properties of 4H-SiC. For example, SiC can more easily be used to fabricate MOSFETs with very high voltage ratings (up to 10 kV), and with lower switching losses. The reliability of SiC power devices is excellent and has continued to improve due to continuing advancements in SiC substrate quality, epitaxial growth capabilities, and device processing. This has enabled the continually accelerating growth of SiC power device commercial adoption. In this talk, I will review the wear-out mechanisms and intrinsic reliability performance of power SiC devices as characterized by time-dependent dielectric breakdown (TDDB), accelerated life test high temperature reverse bias (ALT-HTRB), bias/temperature instability (BTI), terrestrial neutron exposure, and power cycling. I will review some of the known failure mechanisms that have been characterized and addressed through technological advances. I will show qualification data on a wide variety of product families, including discrete devices up to 50 A rated current. Finally, I will show field return data that demonstrates less than 5 FIT (fails per billion device hours) for commercially produced SiC MOSFETs and Schottky diodes, with over 2 trillion device field hours.
Dr. Donald A. Gajewski is the Manager of Reliability and Failure Analysis for Cree Power & RF Advanced Devices, with scope of GaN-on-SiC HEMT-MMICs, SiC power MOSFETs, SiC Schottky power diodes, and SiC power modules. He has been in the semiconductor industry reliability profession for 16 years, with previous tenures at Nitronex, Freescale and Motorola; and experience with technologies including highly integrated silicon CMOS technologies such as SiGe HBT and SmartMOS; magnetoresistive random access memory (MRAM); and advanced packaging such as flip-chip and redistributed chip package (RCP). He completed a National Research Council Postdoctoral Research Fellowship at the National Institute of Standards and Technology, in the Semiconductor Electronics Division, in Gaithersburg, MD. He earned the Ph.D. in physics from the University of California, San Diego, partially under the auspices of a National Science Foundation Fellowship.
Francesco Maria Puglisi
RTN analysis as a tool to link physical device characteristics to electrical reliability in nanoscale devices
Random Telegraph Noise (RTN) is a particular kind of noise consisting in the abrupt and random switch of the measured current/voltage among (two or more) discrete values. It represents a limiting factor for circuit performance and is observed in a variety of devices, despite differences in materials, concept, and manufacturing process. Its origin, still under debate, is attributed to charge trapping/de-trapping into/from defects in the device, which complicates experiments, data analysis, and results interpretation. Still, RTN analysis may contribute key information about device properties, especially for structures that cannot be characterized by classic techniques. However, a standard set of rules to routinely measure, analyze, and interpret RTN is missing. Here, we devise suitable techniques and consider relevant restrictions to enable RTN analysis as a reliable characterization tool. Particularly, we will combine dedicated and careful experiments with refined data analysis and comprehensive physics simulations to establish a complete “value chain” that guarantees reliable results and a correct and insightful physical interpretation. The effectiveness of RTN analysis as an investigation tool will be demonstrated on two different devices, taken as case studies: FinFETs and RRAMs.
Francesco Maria Puglisi received the Ph.D. degree with honor in Information and Communication Technology in 2015 from University of Modena and Reggio Emilia, Italy. During the Ph.D. he was a visiting student at SEMATECH (Albany, NY, USA) and he worked with Gennadi Bersuker on the physics and the reliability of different FET architectures and of novel resistive memories.
He is currently a Research Associate and Adjunct Professor at University of Modena and Reggio Emilia, Italy. His activity focuses on the electrical characterization, physics-based and compact modeling of novel nonvolatile memories, especially RRAM, with a special focus on noise and variability. He is also investigating charge transport, reliability, and noise aspects in novel logic devices such as FinFETs and III-V MOSFETs.
Dr. Puglisi authored and coauthored more than 30 technical papers. He is the recipient of the Best Student Paper Award at the IEEE ICICDT 2013 Conference, 29-31 May 2013, Pavia, Italy and currently serves in the Technical Program Committee of IEEE IRPS conference.
Reliability of power devices
This talk reviews the most relevant dielectric-related trapping mechanisms in GaN-based transistors. Metal-insulator-semiconductor (MIS) devices with partially-recessed gate have been submitted to pulsed and constant voltage stress, with the aim of evaluating the impact of charge trapping processes on the dynamic properties of the devices and on the negative-bias threshold instabilities (NBTI) induced by negative gate bias. Three different dielectrics were considered for this investigation: SiN deposited by rapid thermal chemical vapour deposition (RTCVD), SiN deposited by plasma enhanced atomic layer deposition (PE-ALD), and Al2O3 deposited by atomic layer deposition (ALD). The results obtained within this paper are critically compared to previous literature reports, to provide a more complete view of the state-of-the-art.
He graduated in Electronics Engineering at the University of Padova in 1992 working on the failure mechanism induced by hot-electrons in MESFETs and HEMTs. In 1997 he received the Ph.D. degree in Electrical and Telecommunication Engineering from the University of Padova. Since 2011 is with University of Padova as Full Professor. His research interests involves mainly the electrical characterization, modeling and reliability of several semiconductors devices: a) microwave and optoelectronics devices on III-V and III-N; b) RF-MEMS switches for reconfigurable antenna arrays; c) Electrostatic discharge (ESD) protection structures for CMOS and SMART POWER integrated circuits including ElectroMagnetic interference issues; d) organic semiconductors devices; e) photovoltaic solar cells based on various materials. Within these activities he published more than 700 technical papers (of which about 100 Invited Papers and 10 best paper awards). He has been nominated to IEEE Fellow class 2013, with the following citation: “for contributions to the reliability physics of compound semiconductors devices”.
Reliability-performance evaluation for scaled multi-materials device stacks
Electrical characteristics of new generations of devices combining layers of thin films comprised of metals, oxides, and semiconductor materials are strongly influenced by the charge transfer across the layers. Charge transfer processes are controlled, to a great degree, by the interface regions, their structure and composition being modified by the inter-materials interaction, which is sensitive to stack fabrication conditions. These complex systems pose new challenges for assessing device reliability, which can be affected by even extremely small concentrations of electrically active defects. Electrons injected/generated during device operations or radiation exposure may be temporarily localized by pre- existing defects, giving rise to time-dependent instability of device characteristics caused by charge trapping/de-trapping processes. The rates of these processes strongly depend on their activation energy and are therefore sensitive to the electric field across the material; this suggests that damage evaluation should be performed under application-specific (voltage, temperature) test conditions. We focus on analyzing oxide structural features responsible for charge transfer by combining a variety of electrical measurement techniques with high time and spatial resolutions that allow capturing fast transient charging processes and differentiating signals from different regions through the depth of the multi-layer stacks. These data are used to fit the results of simulations of the physical processes underlying the electrical measurements in order to extract spatial and energy profiles of electrically active centers, thus providing helpful feedback to optimize the device fabrication process. We discuss examples of implementations of this approach for analysis and optimization of a variety of device stacks.
Gennadi Bersuker focuses on physical and electrical characterization and reliability of the semiconductor devices, such as transistors of various scaling/compositions, IIIV logic, nonvolatile and charge trapping memories, etc., with the goal to identify materials atomic/structural features affecting device electrical parameters. He is the Editor of IEEE Transactions on Device Materials and Reliability and has been involved in organizing, chairing, or serving as a committee member in a number of technical conferences, including IRW, IRPS, IEDM, APS, etc. He has published over 350 papers on the electronic properties of dielectrics and semiconductor processing and reliability.
Novel characterization techniques providing reliable and low-power Flash NOR memory operations
With the rise of alternative Non-Volatile Memory technologies, such as Resistive, Phase-Change or Magnetic RAM, Flash NOR technology hardly competes in chasing after low-power memory operations. Because of Hot-Carrier programming principle, the power consumption of single bitcells barely scales along roadmap, leading to increased consumption of denser embedded Flash NOR circuits. Together with low-power optimization, process and integration efforts also particularly focuses on Flash P/E cycling performance, whose impact is even more critical in recent technological nodes because of increased electrical fields and fewer electrons being stored in the floating gate.
This talk will emphasize reliability and power consumption optimization thanks to novel characterization and modelling techniques, aiming to provide optimized operations patterns and thus taking maximum advantage of intrinsic device capability.
We will first present how a priori defined bias patterns allow efficient device operation with respect to standard schemes. After having detailed modelling steps and demonstrating increased operation efficiencies on 40nm Flash NOR single cells, different optimized patterns with different shapes will be compared and analyzed. We will show how a single cell might address different application constraints in term of power consumption and circuit scaling. The impact of optimized operations on device reliability will be addressed in a second part. We will take advantage of the aforementioned technique and equivalent transistor test structures for separating the program- and erase-induced contributions to the overall Flash cycling degradation. Their respective role on power consumption evolution along cycling will also be discussed and, finally, guidelines for low-power and reliable Flash operations provided.
Jean Coignus was born in Toulouse, France, in 1984. He received the M.Sc. and the Ph.D. degrees in Solid-State Physics and Electronic Engineering from the Grenoble Institute of Technology, Grenoble, France, in 2007 and 2010, respectively. His Ph.D. thesis focused on the electrical characterization and quantum modeling of advanced MOS technologies with high-k/metal gate.
From 2011 to 2013, he was responsible for TCAD simulation and electrical characterization of Silicon HeteroJunction (SHJ) solar cells at the French Institute for Solar Energy (Le Bourget-du-Lac, France), from lab scale to pilot-line industrialization and manufacturing.
He joined CEA, LETI (Grenoble, France) in 2013 as a Research Staff member, and since then focuses on non-volatile memory and CMOS electrical characterization and reliability.
He has authored/coauthored 20+ publications, and owns several patents.
Reliability of electronic devices: nanoscale studies based on the conductive atomic force microscope
The conductive atomic force microscope (CAFM) has become one of the most useful techniques to analyze the electronic properties of many materials and electronic devices at the nanoscale. In this presentation I will show the capabilities of the CAFM to study many crucial nanoscale phenomena of thin dielectrics, such as the effect of thermal annealing, polycrystalliztion, thickness fluctuations, local defects, charge trapping and detrapping, stress-induced leakage current, negative bias temperature instability and dielectric breakdown and resistive switching. I will present our last results combining electronic and mechanical CAFM stresses for studying the local properties of thin dielectrics, and I will demonstrate the direct link between resistive switching and mechanical strength, a phenomenon that could be very important in flexible devices. I will focus on HfO2, Al2O3, and SiO2, although I will also present some recent data in two dimensional dielectrics (i.e. hexagonal boron nitride). I will also present how to modify a CAFM to perform advanced experiments, like applying current compliances and collect current vs. time, among others. Finally, I will give you some indications about how to perform reliable experiments and how to avoid wrong CAFM data interpretations.
Mario Lanza is a Young 1000 Talent professor at the Institute of Functional Nano & Soft Materials, at Soochow University. Dr. Lanza got his PhD with honors in 2010 at the Electronic Engineering Department of Universitat Autonoma de Barcelona. During the PhD he was a visiting scholar at The University of Manchester (UK) and he worked on different projects for Infineon Technologies. In 2010 and 2011 he completed a postdoc at Peking University, where he worked on 2D materials, and in 2012 and 2013 he was Marie Curie postdoctoral fellow at Stanford University, where he worked with Paul C. McIntyre and Hongjie Dai. Dr. Lanza has published over 55 research papers, including Science, Advanced Materials, Nanoscale, Applied Physics Letters and IEEE journals, as well as four patents and four book chapters. He is best known for his reliability studies of nanoelectronic devices, especially those using conductive AFM, a field in which he is editing an entire book for Wiley-VCH. Currently, Dr. Lanza is leading a research group formed by two postdocs, ten graduate students and two visiting scholars.
Muhammad A. Alam
The Elegant Complexity of a Simple Capacitor: Revisiting the Reliability Physics of Thick insulators
Over the last decade, the functional integration of non-CMOS components (e.g., MEMS, biosensors, ferroelectric/polymer capacitors, etc.) onto the CMOS fabric has been a defining trend of the semiconductor industry. Predictive, physics-based reliability modeling of these non-CMOS components have been a challenge, because the geometry and operation of these components are often far removed from the historical context, and the classical reliability models do not apply. At Purdue, we have taken a broad view of the emerging field and dedicated ourselves in developing reliability models for More-than-Moore components that are comparable in sophistication and equal in insights to the CMOS reliability models that supported the Moore’s law. In this talk, we will use the reliability physics of thick dielectrics -- broadly used as isolation capacitor, active PV materials, encapsulants, etc. – to illustrate the challenges and opportunities ahead. We will see that once the basic physics of reliability issues are understood, there are intuitively obvious opportunities to address the reliability concerns within an end-to-end hierarchical IC design framework.
Professor Alam teaches Electrical Engineering at Purdue University, where his research focuses on the physics and technology of classical and novel semiconductor devices. Following a decade-long industrial sojourn at Bell Labs, he returned to Purdue in 2004, where he now hold the Jai N. Gupta professorship. Dr. Alam has made fundamental contributions to reliability physics, limits of biosensing and energy conversion, nonlinear percolation, etc. He has published over 250 journal papers and has presented numerous talks at international conferences. He is a fellow of IEEE, American Physical Society, and American Association for the Advancement of Science. He is recipient of 2006 IEEE Kiyo Tomiyasu Medal for contributions to device technology for communication systems and 2015 SRC Technical Excellence Award for contributions to semiconductor industry.
Advances in imaging and quantification of electrical properties at the nanoscale using Scanning Microwave Impedance Microscopy (sMIM)
Understanding and optimizing advanced materials frequently requires detailed knowledge of nanoscale electrical properties. Scanning probe techniques such as scanning tunneling microscopy (STM), conductive AFM (cAFM), scanning capacitance microscopy (SCM), and Kelvin probe force microscopy (KPFM) provide such nano-electrical measurements, but are generally limited in the classes of materials they can characterize or the properties they can measure. Scanning microwave impedance microscopy (sMIM) uses GHz frequency microwaves and shielded AFM probes to directly measure the impedance (capacitance and conductance) of the tip sample interface. As such sMIM is sensitive to the permittivity and conductivity of a wide variety of samples including dielectrics, conductors, and semiconductors.
After introducing the theory of operation, we will review the state of the art, including imaging high-resolution electrical features such as sub 15 nm Moire’ patterns in Graphene, carbon nanotubes of various electrical states , conductivity variations in 2D materials, and structures of microelectronic devices. In addition to imaging, the technique is suited to a variety of metrology applications where specific physical properties are determined quantitatively. We will present research activities on quantitative measurements to determine dielectric constant (permittivity) and conductivity (e.g. dopant concentration) for a range of materials. Examples include bulk dielectrics, low-k dielectric thin films, capacitance standards and doped semiconductors. These experiments include the measurement of nano-scale capacitance vs voltage curves for non-linear materials.
Dr. Friedman has engaged in academic and industrial research in a variety of areas including image processing, surface science, electron optics, bio-medical instrumentation, and bio-physical simulation. He currently serves as CEO of PrimeNano, Inc, a Silicon Valley instrumentation startup focused on commercial implementation of sMIM for research and commercial applications. Before co-founding PrimeNano he founded and led an R&D and systems engineering consulting firm in Silicon Valley helping startups to fortune 500 clients transition complex systems to commercial reality. Prior to that he held R&D, systems architecture and technical leadership roles at Gatan, Inc., Etec Systems, KLA-Tencor, MDS Sciex and Signature Bioscience. He holds a PhD in applied physics from Stanford University, an MPhil in physics from Cambridge University and a BSE in engineering physics from Cornell University.
Yen-Chieh (Kevin) Huang
AC stress & STD cell aging characterization to enhance reliability coverage of logic circuits
One of the major purposes of characterizing device reliability is to provide reasonable margin during design phase. Prevention is always better than a cure from risk control and cost management point of view. Over the last decade, foundry has been asked to provide adequate IP and cell libraries to reduce customers’ product development cycle. Though these libraries were well characterized but their aging behaviors were left to designers’ own judgments. To integrate aging effect into static timing analysis (STA) either for synthesis or post-simulation, one needs a fairly accurate SPICE aging model which covers AC stress and gate level (or standard cell level) timing shift. This demands Si-to-Simulation comparisons which will be addressed in this paper.
Yen-Chieh Huang has engaged in process and OTP IP qualificaton since joining tsmc in 2008. He currently serves as manager of Reliability Test Methodology Development Section, a dedicate small task force focused on bridging the gap between circuit aging and device reliability, e.g. STD cell timing shift, transistor high frequency stress, logic circuit DFT & massive reliability statistics. Before working in tsmc, he was DRAM process integration engineer in Nanya Technology Corporation for 2 years. He received his M.S. in Physics from National Taiwan University in 2006.