Atomistic modeling of defects in SiO2 and HfO2 for reliability predictions
Charge capture and emission by point defects in gate oxides of metal–oxide–semiconductor field-effect transistors (MOSFETs) has been linked to a wide range of detrimental phenomena. These include issues such as random telegraph noise (RTN), 1/f noise and bias temperature instability (BTI). Although these effects have been studied for more than 40 years, their underlying physical mechanisms are still controversial. Their impact on overall device performance becomes ever more prominent as MOSFET sizes scale down and reach nanometer dimensions. Although it is widely accepted that these effects are caused by trapping and release of electrons and holes by defects from a semiconductor channel of an MOSFET (typically Si), the detailed microscopic nature of many of these defects remains unknown.
In recent years, computational modeling has been used in conjunction with experimental data to provide atomistic resolution of a number of processes. In this tutorial, we will focus on the use of atomistic modeling to elucidate the structures of defects involved in reliability issues of electronic devices. We will show how complex amorphous materials can be modeled and how the atomistic and electronic structures of defects in these materials can be extracted. An important aspect of modeling is to be sure that what is calculated is what is actually being measured under experimental conditions. With that in mind, we will show how these models can be compared to experimental data to justify that these are indeed the defects involved in electronic reliability issues.
Al-Moatasem El-Sayed received his Masters in chemistry at the University of Manchester in 2010. He then went on to do his Ph.D in physics at University College, London, focusing on atomistic modeling of point defects in oxides. He currently works between University College, London and the Institute of Microelectronics at the technical university of Vienna further developing techniques to understand the role of defects in microelectronic reliability issues.
This tutorial will cover common failure mechanisms in MEMS and examples of design and process fixes. Also covered will be: lifetime predictive methodologies, acceleration factor development, statistical distributions of reliability data, and case studies of non-standard MEMS reliability predictions. Simulation of MEMS, packaging, and systems will also be included. This tutorial will provide guidance to the MEMS user and/or designer, with advice and how to fix problems before they happen, as well as how to fit data properly.
Ms. Allyson Hartzell is a Managing Engineer at Veryst Engineering with more than three decades of professional experience in emerging technologies. Ms. Hartzell is an internationally recognized expert in MEMS reliability and has expertise in surface chemistry and analytical techniques for failure analysis. Ms. Hartzell possesses a broad background in semiconductor and MEMS fabrication, yield enhancement, emerging technology manufacturing and reliability, packaging materials and processing, and cleanroom science— including particulate and molecular contamination. Ms. Hartzell works with customers on reliability, failure analysis root cause and corrective action, manufacturing problem solving and fundamental materials science.
Prior to joining Veryst Engineering, Ms. Hartzell was Director of Engineering for Reliability, Failure Analysis, and Yield at Pixtronix, a wholly owned subsidiary of Qualcomm. She was a Senior Staff Scientist in Reliability and Yield at Analog Devices Micromachined Products Division, and has worked at IBM and Digital Equipment Corporation.
Plasma induced damage (PID): challenges and overview
Plasma induced damage is a well-known reliability topic since the early 1990. A lot of publications, master and PhD theses as well as books have been published on the topic. Even for today´s technology nodes with very thin oxide layers, high-K dielectrics, SOI or FinFET technologies it is still an issue and not all areas are well understood or covered by standard design rules.
In this tutorial an overview will be given on all different aspects of PID. Especially the layout of interconnects and its effect on MOS devices will be discussed. PID test structures, protection devices, reliability stress measurements, data analysis and sampling will be addressed. The challenges for a complete set of reliability stress measurements for process qualification and for fWLR Monitoring will be pointed out.
This tutorial is suited for engineers and scientists who start in the area of PID. But also experts who already work on this topic will benefit since fail mechanisms are described which are usually not included in a standard set of design rules. Valuable details, international standardisation work and literature citations can be picked up.
Andreas Martin is a process reliability expert in the corporate reliability department of Infineon Technologies AG (IFX) in Neubiberg, Germany. His experience comes from over 23 years in the field of “Wafer Level Reliability” (WLR) on topics such as dielectric reliability, plasma induced damage, fast WLR Monitoring (fWLR), test structure design, reliability stress measurements and data analysis. He is responsible for the IFX process qualification and for the design manual rules on plasma induced damage. He has been tutorial speaker at conferences, such as IEEE IRPS, ESREF, WoDiM, EurosimE, IEEE ICMTS. He is frequently a tutorial speaker on various reliability topics within the IFX University. He is active in standardization work with JEDEC since 20 years on WLR topics and involved with IEC and ITG. In the past he had chaired IEEE IIRW, WoDiM and ITG-Fachtagung and was additionally involved in committee work of IEEE IRPS and ESREF.
Oxide Defects in Emerging Technologies: Characterization and Mitigation
Aggressive scaling of transistor dimensions and introduction of new materials increases the impact of material structures/defects on the device and circuit-level performance and reliability, making technology development more expensive and challenging. It drives the need for robust electrical characterization accounting for material, device, circuit, and system levels specifics of modern transistor technology. An example of III-V semiconductors transistors demonstrates that incomplete assessments of the material characteristics by conventional techniques presents a formidable challenge to implementation of new materials.
Among a number of practical applications requiring novel characterization techniques, we discuss one of the major issues imposing limitations on the operating speed of modern integrated circuits –timing jitter, a deviation of signal timing edges from their “correct” positions. We demonstrate that jitter degradation under operation conditions is caused by specific defects in the materials stacks that opens the options for performance improvement.
To keep up with the progress of electronic technology, currently used standard characterization techniques and methods should evolve accordingly. In particular, there is a gap in evaluating performance and reliability metrics of semiconductor devices with cut-off frequencies higher than 100 GHz. Preliminary results suggest that utilizing electro-optical effects and properties of plasmonic excitations at the interfaces, it is possible to measure electron transport characteristics with sub-picosecond resolution, greatly exceeding existing characterization methods.
Dr. Dmitry Veksler received Ph.D. degree in Physics in 2007 from Rensselaer Polytechnic Institute in Troy, NY. His dissertation was devoted to THz plasmonics, and plasma-wave electronics applications in THz spectroscopy and imaging. In 2009 he joined Electrical and Physical Characterization group at SEMATECH working on electrical characterization, reliability, and modeling of emerging semiconductor devices. In 2015 Dr. Veksler joined Engineering Physics Division at NIST. His current research focus is on characterization of electrically active defects in dielectrics and semiconductors, and investigation of their effects on performance and reliability at the material, device, and circuit levels. He is particularly interested in nonvolatile memories and in 2D material devices (for beyond CMOS applications). Also he is interested in Biosensors, Neural networks, and Solar cells research. Dr. Veksler has authored and co-authored over 100 technical publications in journals and conference proceedings.
SiC MOSFET Reliability – A Similar Elephant but with Different Spots
The development of silicon carbide (SiC) based electronic devices has sometimes been described as “just like silicon, only harder”. While being a wider bandgap material (3.2eV for the 4H-SiC polytype) and mechanically stronger, SiC shares many similarities with silicon. In fact, some of the benefits of SiC as a wide bandgap semiconductor that make it suitable for high-performance power devices and high-temperature devices (such as high critical electric field 10x that of silicon) also create important, albeit surmountable, challenges that must be considered when designing reliable devices.
In this tutorial, we will begin by exploring the electrical properties of SiC and the impact on the performance of MOS-based devices, particularly the expected causes of the relatively poor inversion-layer electron mobility. Then, we will explore the intrinsic reliability of thick gate oxides used in SiC power devices, which has been demonstrated to be suitable for long-term reliability. Finally, we will investigate some of the practical challenges to achieve acceptable gate oxide reliability in production of SiC MOSFET devices. Throughout the presentation, I will strive to highlight the similarities to silicon devices and raise awareness of the critical differences that we must consider to ensure high performance and high reliability of SiC MOSFETs.
Over the past 15 years, Kevin has developed high-performance wide-bandgap semiconductor devices, specifically SiC power MOSFETs. He received his PhD in Electrical Engineering from Rensselaer Polytechnic Institute by developing some of the first GaN based power MOSFETs. Kevin then spent 10 years at General Electric, leading GE's SiC power MOSFET development, including internal and government projects. Subsequently, he joined SemiSouth where he served as Vice President of Product Development to commercialize SiC Schottky diodes and SiC JFETs. During his time in the field of SiC power devices, his work with academic, industrial and government institutions has focused on developing new designs and processes for reliable, high-performance SiC power MOSFETs. He has been honored with invited presentations on the topic of SiC MOSFET technology. Kevin has been granted 17 patents and has authored over 80 papers and presentations.
Scaling and Variability Challenges to Advance Node BEOL Reliability
As scaling of the critical pitch in semiconductor devices and interconnects advances from technology node to technology node, the impact of process variability becomes the paramount challenge to ensuring the necessary BEOL extrinisic and intrinsic reliability. Factors contributing to this situation stem from fundamental lithography capability, variability of key processes like RIE and CMP, and materials that are increasingly selected for electrical properties, which often increase the challenge associated with both manufacturability and mechanical robustness. To address these challenges existing reliability methodologies must evolve to address die- and wafer-level variability, process interaction with design, as well as to be more predictive of both intrinsic wear-out and reliability limiting defectivity at actual operating conditions. In this tutorial the impact of key processes and their inherent variability on reliability will be reviewed. The tutorial will also focus to advancements to methodologies to address some of these challenges.
Dr. Patrick Justison received his Ph.D. and M.S.E. in materials science from the University of Texas and his B.S. in materials science from Lehigh University. He has been with GLOBALFOUNDRIES since its inception in 2009, after joining AMD in 2008. He currently the leads the BEoL reliability team in Malta, NY. He and his team are responsible for all aspects of interconnect reliability, including development, qualification, PDK support, and development of novel methodologies for advanced technology nodes. Previously, he was with Freescale in Austin, TX where he also focused on BEoL reliability topics
Sunday Night Tutorial: Imaging the Antikythera Mechanism
In 1900, a party of sponge divers chanced on the wreck of a Roman merchant vessel between Crete and mainland Greece. It was found to contain numerous ancient Greek treasures, among them a mysterious lump of clay that split open to reveal ‘mathematical gears’, now known as the Antikythera Mechanism. In 2005 we travelled to the National Archeological Museum in Athens to apply our Reflectance Imaging methods to the mechanism in hopes of revealing ancient writing on the device. We were successful, and along with the results of Microfocus CT imaging, epigraphers were able to decipher 3000 characters compared with the original 800 known. This lead to an understanding that the device was a mechanical, astronomical computer, built around 150 B.C.E., capable of predicting solar and lunar eclipses along with other celestial events. This talk will overview both the imaging methods along with what they reveal about the Antikythera Mechanism.
Tom Malzbender is a senior research scientist who just ended a 31 year career at Hewlett-Packard Laboratories in March and is now an independent consultant. Tom works at the intersection of computer graphics, computer vision and signal processing and has developed the techniques of Reflectance Transformation, Polynomial Texture Mapping (PTM) and Fourier Volume Rendering. He also developed the capacitive sensing technology that allowed HP to penetrate the consumer graphics tablet market. His PTM methods are used by the National Gallery in London, the Tate Gallery and in the fields of criminal forensics, paleontology and archeology. Tom is on the program committees for several 3D graphics and vision conferences. More information can be found at sites.google.com/site/tommalzbender/
Scalpel SPM toward the three-dimensional characterization of confined volumes
Three dimensional (3D) device architectures and novel materials has been already widely introduced to maintain scaling and performance improvement in nowadays microelectronics. Logic switches (transistors) have been the first to move from 2D to 3D in 2011 with the introduction of FinFET in replacement of planar devices. Nonvolatile memory has followed in 2014 with the replacement of traditional flash devices with 3D NAND. Finally, the requirements for future technology nodes foresee the introduction of new materials (such as III-V compound semiconductors) fully integrated in 3D structures (trenches) embedded in traditional Si substrates. However, the pervasive introduction of 3D devices poses unparalleled challenges to semiconductor metrology. We present in this lecture Scalpel SPM as a concept for three-dimensional characterization with nm spatial resolution using scanning probe microscopy (SPM). Based on a 2D contact-mode SPM using a (biased) conductive tip. In Scalpel SPM we extend this method to 3D by combining the high lateral resolution conductance mapping with a controlled material removal during tip scanning. The consecutive planar SPM images are then stacked and interpolated for the formation of the 3D tomogram. After a detailed introduction of the basic principles and practical experimental conditions to perform Scalpel SPM, this tutorial discusses a broad set of applications for electronic materials with emphasis on filamentary-based resistive switching, 3D NAND, failure analysis to name a few.
The author acknowledges the Research Foundation - Flanders (FWO) for the partial funding of this research.
Umberto Celano received his B.Eng. in Electronic Engineering and a M.Sc. degree in Nanoelectronics with honors from the University of Rome “Sapienza”, Italy in 2009 and 2011 respectively. He holds a Ph.D. degree in Physics from the KU Leuven, Belgium. In 2010, he joined imec in Belgium for his M.Sc. thesis, working on the chemical and electrical analysis of high-k dielectrics for sub-30 nanometer transistors node. One year later, he started a Ph.D. at KU Leuven performing his research at imec on ionic devices for non-volatile memory. In 2013, Umberto visited Osaka University in Japan, where he collaborated on the design of nanocellulose-based devices. In 2015 Umberto’s Ph.D. dissertation has been awarded by the faculty of Science of KU Leuven with an honorable mention and selected for publication as a book by Springer. Umberto is the recipient of the Rogen A. Haken Best Paper Award at IEDM (2013) and has authored or co-authored 50+ papers in international journals and conference proceedings. Currently, Umberto is a research scientist in the material and component analysis group of imec. His research interests include nanometer scale issues in materials, emerging nanoelectronics and physical characterization. His goal is to explore methods and novel metrology techniques that enable the understanding of the physics in nanomaterials and nanoelectronics devices.