Fallen Leaf Lake
2015 IIRW Schedule

2017 IEEE International Integrated Reliability Workshop


SUNDAY, October 8 Please have lunch before arriving at the camp; no lunch will be served at the camp.

3:00-6:00 p.m. Registration: Pick up badges, electronic handout, and attendee gift; Discussion Group and SIG Signup (Lodge Lounge)

3:00-8:00 p.m. Lodge check-in: Get room assignment (prearranged) & room key. (If physically challenged, please notify desk of special needs.)

6:00-7:30 p.m. DINNER (Dining Room)

7:30-8:30 p.m. Sunday Night Tutorial (Angora Room) Last Minute Change: We will show the PBS documentary “Transistorized!”

8:30-10:00 p.m. Social (Old Lodge)


MONDAY, October 9

7:00-8:00 a.m. BREAKFAST (Dining Room)

Plenary Session (Angora Room)

8:00-8:10 a.m. Welcome & Introduction— Tom Kopley, ON Semiconductor

8:10-8:20 a.m. Technical Program Overview— Luca Larcher, Univ. of Modena and Reggio Emilia

8:20-9:20 a.m. Keynote: Electrified Driving Experience - Expectations on Automotive Semiconductors — Hans Stork, ON Semiconductor

Session #1 (Angora Room) — PV Device Reliability - Electromigration, Chair: Tom Kopley, ON Semiconductor

9:20-9:50 a.m. 1.1 (INVITED) Compact modeling for reliability simulation— Andries Scholten, NXP Semiconductors.

9:50-10:20 a.m. Coffee and Snack Break

10:20-11:20 a.m. Tutorial # 1: The Reliability of Thin Film Photovoltaic Devices and Emerging PV Materials — Vikram Dalal, Iowa State Univ.

11:20-11:45 a.m. 1.2 Electromigration: Lognormal versus Weibull Distribution — Adarsh Basavalingappa, Jennifer M. Passage, Ming Y. Shen, and James R. Lloyd, SUNY Polytechnic Institute

12:00-1:00 p.m. LUNCH (Dining Room)

1:00-1:05 p.m. Announcements (Angora Room)

Session #2 (Angora Room) Advanced Characterization, Chair: Luca Larcher, University of Modena and Reggio Emilia

1:05-2:05 p.m. Tutorial #2 Electron Paramagnetic Resonance: What on Earth are you Talking About? — Jason T. Ryan, National Institute of Standards and Technology

2:05-2:30 p.m. 2.1 Fast TDDB monitoring for BEOL interconnect dielectrics — C. LaRow, Z. Chbili, S. F. Yap, A. Kerber, T. Nigam, GLOBALFOUNDRIES Inc

2:30-2:55 p.m.

3:00-3:30 p.m. Coffee and Snack Break

Session #3 (Angora Room)FET Reliability, Chair: Patrick Lenaham, The Pennsylvania State University

3:30-3:55 p.m. 3.1 (INVITED) Reliability of FinFET Devices — Anisur Rahman, Intel Corporation

3:55-4:35 p.m. 3.2 Self-heating measurement methodologies and their assesment on bulk FinFET devices — P. Paliwoda, Z. Chbili, A. Kerber, A. Gondal, D. Misra, GLOBALFOUNDRIES Inc

4:35-5:00 p.m. 3.3 Random Dopant Fluctuation Variability in Scaled InGaAs Dual-Gate Ultra-Thin Body MOSFETs: Source and Drain Doping Effect — Nicolò Zagni, Francesco Maria Puglisi, Giovanni Verzellesi and Paolo Pavan, Univ. of Modena and Reggio Emilia

5:00-5:25 p.m. 3.4 (Late News) A New Approach for MOSFET Interface Defect Characterization: High, Ultra-low, and Zero Magnetic Field Spin Dependent Charge Pumping— Mark Anders, Patrick Lenahan and Aivars Lelis. The Pennsylvania State University and U.S. Army Research Laboratory

5:25-5:55 p.m. Discussion Group Overview (Angora Room)

6:00-7:30 p.m. DINNER (Dining Room)

7:30-9:00 p.m. Poster Session (Cathedral Room), Chair: Jason Campbell, NIST

9:00-10:00 p.m. Social (Old Lodge)


TUESDAY, October 10

7:00-8:00 a.m. BREAKFAST (Dining Room)

8:00-8:05 a.m. Announcements (Angora Room)

Session #4 (Angora Room)Package, Chair: Jason Campbell, NIST

8:05-9:05 a.m. Tutorial #3: An Overview of Chip to Package Interaction and its Impact on Reliability — Scott Pozder, GLOBALFOUNDRIES

9:05-9:30 a.m. 4.2 Integrated Solder Bump Electromigration Test Chip and Coupon Cards for the Characterization of Pb-free SAC Solders Under Stress — M. Ring, D. Noble, B. McGowan, T.E. Kopley, J.R.Lloyd, ON Semiconductor, SUNY Polytechnical Institute

9:30-10:10 a.m. 4.2 (INVITED) Optimal Design Rule and Reliability of Chip-to-Package Interaction — In Hak Baick, Samsung

10:10-10:40a.m. Coffee and Snack Break

10:40-11:05 a.m. 4.3 Wafer Level EDMR with Spatial Resolution Capabilities: Magnetic Resonance in a Probing Station — Duane McCrory, Jason Campbell, Mark Anders, Jason Ryan, Pragya Shrestha, Kin Cheung and Patrick Lenahan, The Pennsylvania State University

11:10-11:40 a.m. GROUP PICTURE

12:00-1:00 p.m. LUNCH (Dining Room)

1:00-1:05 p.m. Announcements (Angora Room)

Session #5 (Angora Room) — High Voltage Devices, Chair: Brad Bittel, INTEL

1:05-1:45 p.m. 5.1 (INVITED) SiC MOSFET Reliability Issues and Implications for Qualification Testing — Aivars Lelis, U.S Army Research Laboratory

1:45-2:10 p.m. 5.2 Threshold voltage hysteresis in SiC MOSFETs and its impact on circuit operation — Katja Puschkarsky, Hans Reisinger, Thomas Aichinger, Wolfgang Gustin and Tibor Grasser, Infineon Technologies, Vienna University of Technology

2:10-2:50 p.m. 5.3 (INVITED) Coupled experimental/simulation analysis as a tool for probing trap-related and high-electric-field phenomena in GaN HEMTs— Giovanni Verzellesi, Univ. of Modena and Reggio Emilia

2:50-3:15 p.m. 5.4 Influence of lucky defects distributions on Early TDDB Failures in SiC Power MOSFETs — J. Chbili, Z. Chbili, A. Matsuda, K. P. Cheung, J. T. Ryan, J. P. Campbell, M. Lahbabi, National Institute for Materials Science

3:15-3:45 p.m. Coffee and Snack Break

Session #6 (Angora Room) — Flash Memory, Chair: Jean Yang-Scharlotta, Jet Propulsion Laboratory

3:45-4:10 p.m. 6.1 Impact of CMOS Post Nitridation Annealing on Reliability of 40nm 512kB Embedded Flash Array — Thibault Kempf, Marc Mantelli, François Maugain, Arnaud Regnier, Jean-Michel Portal, Pascal Masson, Jean-Michel Moragues, Marjorie Hesse, Vincenzo della Marca, Franck Julien1, Stephan Niel, STMicroelectronics, 2IM2NP, Aix-Marseille University, EpOC / Nice Sophia-Antipolis University

4:10-4:50 p.m. 6.2 (INVITED) 2D vs 3D NAND Technology: A Reliability Benchmark — Giuseppina Puzzilli, Micron Technology, Inc

4:50-5:15 p.m. 6.3 Effect of radiation, temperature and endurance on pulsed programming of commercial NAND Flash memory — Avyaya Jayanthi Narasimham, Andrew Anthony Gonzalez and Jean Yang-Scharlotta, Jet Propulsion Laboratory, California Institute of Technology

6:00-7:30 p.m. DINNER (Dining Room)


WEDNESDAY, October 11

7:00-8:00 a.m. BREAKFAST (Dining Room)

8:00-8:05 a.m. Announcements (Angora Room)

Session #7 (Angora Room) — Advanced Modeling, Chair: Luca Larcher, University of Modena and Reggio Emilia

8:05-9:05 a.m. Tutorial #4: Atomistic Calculations for Material and Device Reliability — Alex Shluger, Univ. College London

9:05-9:45 a.m. 7.1 (INVITED) Accurate prediction of device reliability from fundamental properties of point defects in dielectric stacks — Dipankar Pramanik, MDLSoft Inc

9:45-10:25 a.m. 7.2 (INVITED) Realistic model of BEOL and MOL TDDB — Patrick Justison, GLOBALFOUNDRIES, Inc.

10:25-10:50 a.m. Coffee and Snack Break

10:50-11:50 a.m. Tutorial #5: Integrated Photonics Packaging Reliability – Assessing Packaging Strategies and Reliability Testing: Evaluating current passive fiber alignment packaging trends and how to test them — Martin Anselm, Rochester Institute of Technology

12:00-1:00 p.m. LUNCH (Dining Room)

1:10-6:00 p.m. Open—The afternoon is free for discussion, hiking & other recreation. All attendees are required to be back before dark.

6:00-7:30 p.m. DINNER (Dining Room)

7:30-8:30 p.m. Poster Session (Cathedral Room), Chair: Charles LaRow, GLOBALFOUNDRIES Inc

8:30-9:30 p.m. Discussion Groups: Chair:

THURSDAY, October 12

7:00-8:00 a.m. BREAKFAST (Dining Room)

8:00-8:05 a.m. Announcements (Angora Room)

Session #8 (Angora Room) — Novel Device & Memory, Chair: Patrick Lenaham, The Pennsylvania State University

8:05-9:05 a.m. Tutorial #6: Embedded Ferroelectric Memory – Operation, Reliability, and Applications — Ted Moise, Texas Instruments

9:05-9:45 a.m. 8.2 (INVITED) Negative Capacitance Transistors — Sayeef Salahuddin, University of California, Berkeley

9:45-10:15 a.m. Coffee and Snack Break / Check Out of Room

10:15-11:05 a.m. 8.3 (INVITED) Reliability Aspects of Novel Anti-Ferroelectric Non-Volatile Memories Compared to Hafnia based Ferroelectric Memories — Milan Pèsic, NaMLab GmbH

11:05-12:00 a.m. DG Summary / SIG Report / Wrap-up

12:00-1:00 p.m. LUNCH (Dining Room) & then the Workshop Ends

1:00 p.m. Shuttle Bus to San Francisco International Airport leaves Stanford Sierra Camp


Poster Presentations


Refereed Posters

RP01 Silicon dioxide degradation in strongly non-uniform electric field - Yuri Tkachev and James A. Walls. Silicon Storage Technology, Inc.

RP02 Study of HTO-based alternative gate oxides for high voltage transistors on advanced eNVM technology - Dann Morillon, Clement Pribat, Franck Julien, Nathalie Cherault, Jerome Goy, Olivier Gourhant, Jean-Luc Ogier, Pascal Masson, Giada Ghezzi, Yhibault Kempf, Julien Delalleau, Alexandre Villaret, Jean-Christophe Grenier, Stephan Niel. STMicroelectronics.

RP03 Impact of Hot Carrier Stress on Small-Signal Parameters of FD SOI NMOSFETs - T. Chohan, S. Slesazeck, J. Trommer, S.Lehmann, A. Pakfar, D. Harame, T. Mikolajick. NaMLab gGmbH, GLOBALFOUNDRIES.

RP04 Threshold Voltage Instability Assessment of Zinc Oxide Thin-Film Transistors with an Al2O3 Gate Dielectric - R. A. Rodriguez-Davila, C. E. Osborne, M. Quevedo-Lopez, and C. D. Young. University of Texas at Dallas. (Late news)

RP05 Time Dependent Dielectric Breakdown at Ultra Low Frequencies in Low-K Dielectrics - Austin M Thomas, J.M. Passage, and J.R. Lloyd. SUNY Polytechnic Institute, College of Nanoscale Science. (Late news)


Open Posters

OP01 A Finite Element Method for Modeling Void Growth in Electromigration Failure Process - Hengyang Zhao and Sheldon Tan. University of California, Riverside.

OP02 A Lifetime and Power Sensitive Design Optimization Framework for Radio Frequency Circuit - Kexin Yang, Taizhi Liu, Rui Zhang, Linda Milor. School of Electrical and Computer Engineering, Georgia Institute of Technology.

OP03 Reliability of Al2O3-SiO2 dielectric stack - Greg Hunsinger, Y. Hoong, Yosef Raskin, Michael Lisiansky, Yakov Roizin, TowerJazz and Technion.

OP04 Modeling of the Reliability Degradation of a FinFET-based SRAM Due to Bias Temperature Instability, Hot Carrier Injection, and Gate Oxide Breakdown - Rui Zhang, Taizhi Liu, Kexin Yang and Linda Milor. School of Electrical and Computer Engineering, Georgia Institute of Technology.

OP05 Wafer-Level Testing Method Influences on UIS SOA Determination - M. Ring. ON Semiconductor.

OP06 Effect of Fabrication-associated Moisture Exposure on ReRAM Device Performance - Karsten Beckmann, Joshua S. Holt, Sierra Russell, Nadia Suguitan, Nathaniel C. Cady, Joseph Van Nostrand. SUNY Polytechnic Institute, Air Force Research Laboratory.

OP07 TiO2/SiOX bilayer insulating stacks for filamentary/distributed resistive switching - Na Xiao, Marco A.Villena, Xu Jing, Fei Hui, Yuanyuan Shi and Mario Lanza. Institute of Functional Nano& Soft Materials, Soochow University.