late registration fee applied this yr.

aka Wafer Level Reliability Workshop







IRW 2005 · October 17-20, 2005
Stanford Sierra Conference Center, Fallen Leaf Lake, California

schedule->   announcement ->

    The Integrated Reliability Workshop focuses on ensuring semiconductor reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the root cause defects and physical mechanisms responsible for reliability problems. It provides a unique environment for understanding, developing, and sharing reliability technology for present and future semiconductor applications as well as ample opportunity for discussions and interactions with colleagues.

    Hot reliability topics for the workshop include: high-κ and nitrided SiO2 gate dielectrics, product reliability and burn-in, NBTI, Cu interconnects and low-κ dielectrics, reliability modeling and simulation, SiGe and strained Si, III-V, SOI, optoelectronics, single event upsets, and reliability assessment of novel devices and future "nano"-technologies



Latest travel and accommodations information
Location: Stanford Sierra Camp, Fallen Leaf Lake, Calif.
getting there from Reno, Nevada: South Tahoe Express
driving there from Reno Airport: (directions) in 14 steps
weather links and sky cam of South lake Tahoe



IRW is sponsored by the IEEE Electron Device Society and the IEEE Reliability Society


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