IIRW 2006 Tutorials
Paul Nicollian, TI
Sufi Zafar, IBM
Christine Hau-Riege, AMD
Tom Remmel, Freescale
Yi Ma, Applied Materials
Andreas Preussger, Infineon
Sujin Ahn, Samsung
Albert J.P. Theuwissen, Dalsa
SiON Gate Dielectric Reliability
Paul Nicollian, TI
SiON films continue to be the choice gate dielectrics for high performance CMOS. Driven by the relentless race to achieve increasingly aggressive performance targets, the continued scaling of electrical thickness is now compounded by the slowing of voltage scaling. This has resulted in the erosion of reliability margins to razor thin levels, requiring an increasingly sophisticated understanding of the degradation physics of these films. In this tutorial, we will discuss the advancements and issues in breakdown mechanisms and lifetime modeling that are important for enabling deeply scaled SiON films to meet challenging high performance reliability requirements.
The Negative Bias Temperature Instability in MOS Devices
Sufi Zafar, IBM
TEL: +1-914-945-3301 FAX: +1-914-945-2141 email:szafar(!at)us.ibm.com
Negative bias temperature instability (NBTI) has become an increasingly important reliability issue for advanced CMOS technology. In the present tutorial, the experimental and theoretical understanding of NBTI will be reviewed. This tutorial will be organized as follows: Section I will review the experimental observations which characterize NBTI. This section will discuss the dependence of NBTI on stress conditions including measurement methdologies. The dependency of NBTI on process conditions will also be discussed. Section II will review various models, comparing the various theories proposed for NBTI. Section III will discuss the practical implications of NBTI, including the performance degradation of circuits. Section IV will discuss the implications for new gate-stack materials. Finally, Section V will summarize some of the many open questions.
Sufi Zafar received her Ph.D. in physics from Syracuse University in 1991. She currently works at IBM T.J. Watson Research Center, Yorktown Heights, N.Y. Her main research areas are experimental and modeling studies of the electrical properties of high permittivity metal oxide films for gate dielectric and memory applications. She has also worked on hydrogenated amorphous silicon and germanium films for solar cell applications. In addition, she has an interest in biophysics, in particular on the potential application of microelectronics to areas of life science. She has published 32 first authored and over 22 coauthored publications. She has received the Materials Research Society Graduate Student Award and an IBM Research Division Award.
Current Challenges in Cu Electromigration Reliability
In today's integrated circuit (IC), more than a kilometer of metal interconnects are required to build a single microprocessor, so that many billions of metal segments exist in each IC. These metal segments are a significant reliability concern due mainly to electromigration. This concern increases with each new generation of microprocessor, which requires the use of a larger number of narrower interconnects, stressed at increasing current densities. This tutorial will address the basics of Cu electromigration and current routes for improved reliability.
obtained her BS and PhD degrees from the department of Material Science and
Engineering at MIT in '96 and '00,
respectively. She worked at Intel as a BEOL reliability engineer in
Reliability Aspects of Integrating High-K Dielectrics into Back-End-of-Line (BEOL) Process Technology
Tom Remmel, James Walls and Douglas Roberts
Technology Solutions Organization
The demand to provide increased integrated circuit functionality at continually decreasing prices is driving the integration of more and more components on-chip. This on-chip migration now includes the incorporation of passive elements directly into the integrated circuit process flow; elements that were previously resident off-chip. Common integrated passive devices include discrete components such as inductors, capacitors and resistors, but could also include resonators, filters, and even optical components. Because of their nature, these devices are usually integrated within or on top of the multi-level metallization. Several of these devices are fabricated using high dielectric constant (high-K) materials. Integrating these materials on-chip presents an array of challenges, including multi-dimensional trade-offs between materials selection, unit process definition, insertion point into the process flow, electrical performance, defectivity, yield and reliability. This paper will focus on the opportunities and trade-offs of integrating high dielectric constant materials into the back-end-of-line process. Throughout the development process, reliability is the key metric which drives many of the decisions.
New Challenges and Requirements to Reliability Research and Development in Semiconductor Technology Evolution
Sr. Manager of Advanced Application Development
Front End Product division
974 E. Arques Ave
Sunnyvale, California, 94086, USA
Semiconductor technology has made significant progress in the past decade. Device dimension has been down scaled to sub-nanometer range. The progress is primarily driven by market force, products with higher performance and lower cost. In the mean time, the semiconductor product market has shifted to more diversified consumer products versus conventional enterprise products. The trend added more complexity and uncertainty of technology direction, the pressure to deliver product to market on time has been heightened. As a result, numerous new materials, new process integration schemes and new design concepts have been developed and implemented to meet the technology demands. Reliability research and development has been significant part of the vicious technology progress. In this talk, I’ll explore challenges and requirements Reliability community will face in the coming technology generations from a technology engineering point of view. I’ll discuss how technology development cycle and cost can be reduced if impacts of material and process integration on reliability are understood at early stage of technology development. I’ll also explain why developing new methodologies and establishing new reliability standards are critical to early technology adoption by design community and market place.
Yi Ma is a Senior
Manager of Advanced Application Development at Applied Materials. His primary responsibility is to explore new
applications in Logic and Flash memory technologies for market share expansion.
He has been working on gate stack engineering, particularly in the areas of
hi-k, nitrided oxide, laser anneal and poly gate
grain structure engineering. His latest
passion is in the area of nano-crystal memory
devices. Prior to joining Applied
Materials in 2002, Yi Ma was a member of technical staff at Technology R&D
Labs of Agere Systems, formerly Bell Laboratories of
Lucent Technologies, where he led the FEOL thermal process development of 350
nm and down to 90 nm CMOS technologies. Yi Ma received a Ph.D
in Physics from
Strategy of Future Reliability Qualification
Tel:+49 89 234 86087, email: Andreas.preussger(!at)infineon.com
The most efficient qualification strategy has become a major part of successful development of products and technologies. The boundary conditions for reliability have become tighter and the dependency between product design, technology and reliability performance has been increased. The discussion on this topic has now reached the community working on standards and guidelines. Qualification standards from the old age work with lists of stress tests that have to be performed to demonstrate the reliability of a product. They give fixed test times and gating criteria like “no fail out of a sample of some ten parts” to be tested mostly in a black box approach, where the failure mechanism is not known because the test ends typically before the first failure is activated.
One example of a standard describing such a procedure is the AEC-Q100, a stress test driven approach which has been created by the Automotive Electronic Council (AEC). It describes a stress test driven qualification approach. Similar standards exist from JEDEC and Telcordia. These standards were needed to improve the quality level at IC manufacturers, their suppliers and the OEMs which were in the range of percents in the late seventies.
Today’s products and especially new technologies following the Technology Roadmap are facing certain new challenges that are not covered by old stress test driven qualification approaches.
Complexity of technologies and products is increasing per technology node and per product generation. The products are covering more functions within one IC.
This improving can only be achieved by better performance of the technologies used to build the products. These improvements on the technology side can only be achieved by changing the materials with an increasing frequency which means that the rate of introduction of new materials to be introduced as solutions for upcoming problems will be dramatically increasing. Therefore the time for development, implementation and learning with these new materials becomes shorter and shorter.
In this context the term qualification has to be redefined.
The development from the old stress based approach to modern strategies like knowledge based qualification using robustness validation are presented in the tutorial together with some application examples how robustness of products could be measured based on technology. Application areas which do not follow these new approaches run the risk to loose contact to the state-of-art technologies.
The present example of via reliability is used to explain what methodologies could be used to find the trade off between performance, design and reliability
Many design challenges are linked to reliability. Tools offered by EDA vendors are now able to do design optimization with respect to yield and reliability as an integrated part of the standard design flow. The integration of the reliability tools is typically done in a partnership between EDA vendor and chip manufacturer. Examples will be presented.
Andreas Preussger received his diploma in physics from the Technical University Aachen in 1980 and the doctor rer. nat. degree from the same university in 1986. From 1986 he worked on the development of smart power, BICMOS and integrated sensor technologies at the laboratories of Siemens AG, Munich, Germany. He holds one of the main patents of Siemens on field of smart power. Since 1992 he is engaged in reliability physics. He raised the central reliability lab for the development of reliability methods and the qualification of all Si-technologies at Infineon and the foundries working for the company. Until 2000 he was director of the technology reliability department. He is now working on the field of quality and process management. He was or is member of the program committees of the IRW, IRPS, ESREF, ICMTS, and Infineon member of JEDEC 14, the Reliability Technology Advisory Board of Sematech and the Robustness Validation Working Goupt of ZVEI and SAE.
Phase Change Memory Reliability
Su Jin Ahn
Technology Development Team #2
Memory Division, Semiconductor Business
Samsung Electronics Co., LTD.
Phase Change Memory (PRAM) is considered to be one of the viable candidates for the next generation to solve the problems and intrinsic scaling limits of conventional nonvolatile memory. Recently, there have been great advances in PRAM development including new phase change materials, various device structures, process technology innovations, and device designs. This tutorial will introduce operation principles of PRAM exploiting new memory material called chalcogenide and then report the reliability considerations to become commercial products. The reliability issues are disturbance immunity, cycling endurance, data retention and degradation related to back-end process. The experiments have been performed by using 256Mb-density device and the observed degradation modes and underlying physical mechanism have been discussed.
Su Jin Ahn received the M.S.
and Ph.D. degrees in electronics and electrical engineering from Pohang University of Science and Technology,
Reliability of On-The-Shelf Stored Image Sensors
prof.dr.ir. Albert J.P. Theuwissen
An aging effect in solid-state image sensors is studied: the generation of hard errors resulting in hot spots or white pixels. These effects manifest themselves as an increase in dark current, a loss in transfer efficiency (in the case of CCDs) and in extra "hot spots". The effects even occur in sensors that are stored on the shelf. It is well known in the imaging community that image sensors are subject to a degradation effect due to radiation. For instance devices intended for space application are fabricated in special processes so that the sensors can withstand radiation or to make them radiation-hard. The question is whether similar effects are also responsible for the creation of hot pixels during normal on-the-shelf storage of image sensors. Simply storing imaging devices on the shelf does indeed result in a few extra hot spots in the picture taken at a later time. It is important to point out that these hot spots or leaky pixels are permanent. They are not a soft error, in the sense that a high-energy particle is absorbed in the silicon, generates a cloud of charge carriers and after the next image all effects are gone. The effects investigated in this study are hard errors: once they are created, they remain present in the imagers. This tutorial describes experiments that are conducted to prove that the main origin can be found with neutrons that are part of terrestrial cosmic rays.
Albert J.P. Theuwissen received the degree in electrical engineering from the Catholic
University of Leuven (