Managment Committee
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Program Announcement/Technical Program
author's instruction for Oral presentations
author's instruction for poster presentations
audio-visual instructions
Stanford Sierra Conference Center
aka Wafer Level Reliability Workshop
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JEDEC

2006 submission deadline was extended to July 22nd
Submissions after July 22nd will be considered as Late News papers
Submission deadline for Late News papers is September 5th, 2006

IRW 2006 · October 16-19, 2006
Stanford Sierra Conference Center, Fallen Leaf Lake, California

Attendees group picture (pdf 2.2 MB)

The 2006 Integrated Reliability Workshop covered a wide and well balanced spectrum of pressing reliability challenges, preparing attendees for reliability problems at hand and those to come. The focus points reflected by this year’s program included gate dielectric reliability, transistor reliability including NBTI and hot carrier aging, interconnect reliability covering metal line and via electromigration and stress migration, wafer level reliability, passive reliability for mixed signal, memory reliability, as well as product reliability.

This year’s workshop featured eight tutorials by world leading experts. Topics included dielectric reliability, NBTI, interconnect reliability including Cu electromigration and integrating high-k dielectrics into BEOL process, memory reliability, imager and sensor reliability, new reliability challenges, and qualification strategy. The tutorials were presented in two parallel sessions on Monday afternoon.

Our keynote on Tuesday morning was given by Dr. Jose Antonio Maiz, Intel Fellow, Director of Logic Technology Quality & Reliability, Intel Corporation on “Reliability Challenges: Preventing Them from Becoming Limiters to Technology Scaling”.