SiC MOSFET Reliability Issues and Implications for Qualification Testing
There are a number of potential reliability issues associated with SiC power MOSFETs, including threshold-voltage stability, gate-oxide reliability, body-diode robustness, short-circuit current robustness, and radiation effects. This talk is primarily focused on threshold-voltage stability and the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold-voltage stability is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct-tunneling mechanism in response to changes in gate bias. This time dependence is not properly accounted for in the existing test methods for assessing high-temperature gate-bias (HTGB) effects, which allow temporary removal of bias during cool down and significant un-biased delay (up to 96 hours) before the post-stress measurements are performed. However, this delay, introduced to accommodate the practical constraints of industrial testing, renders this test practically meaningless due to the significant recovery that occurs in the charge states of the near-interfacial oxide traps. This difficulty can be overcome by reapplying the gate bias for a brief period of time before measuring. Details of the nature of the near-interfacial oxide traps will be discussed, including their activation energy. All this work will be presented within the context of standards development within JEDEC, and a new SiC power-devices qualification working group.
Dr. Aivars Lelis, who received his Ph. D. in Reliability Engineering from the University of Maryland in 2011 and his M.S. degree in Electrical Engineering from the Johns Hopkins University in 2000, leads the Wide Bandgap Device Reliability Team of the Power Conditioning Branch at the U.S. Army Research Laboratory in Adelphi, MD, with a focus on the device reliability physics of SiC and GaN MIS-based power devices, for high-temperature, high-efficiency power conversion and conditioning for advanced Army systems.
Kong Boon Yeap
Realistic model of BEOL and MOL TDDB
In this study, the BEOL and MOL TDDB failure rate integration method is developed and verified, using: (a) long term package level tests on test structures for each failure mode; and (b) circuit level tests on SRAM and logic cells. The failure rate integration method determines the product realistic failure rate based on high volume manufacturing data. We will further demonstrate that product realistic failure rate has little to no impact from changing the voltage acceleration models, as long as the spacing variation is the dominant factor in the product failure rate.
Kong Boon Yeap received the Ph.D. degree in mechanics of materials from the National University of Singapore, Singapore, in 2009. He was a Post-Doctoral Researcher with the Fraunhofer Institute, Munich, Germany, with expertise in the field of nanomechanics, materials science, and reliability of semiconductor research. He is currently with GLOBALFOUNDRIES, Malta, NY, USA, as a Reliability Engineer, focusing on time-dependent dielectrics breakdown of back-end-of-line and middle of line, and circuit level reliability. He has published more than 50 technical papers in international journals and conference proceedings, in the area of material science and reliability engineering.
Reliability of FinFET Devices
Tri-gate transistor architecture represents a radical departure from that of traditional planar transistors. Due to the 3D features associated with their vertical narrow fin, the tri-gate transistor can interact with traditional reliability mechanisms in new ways. The goal of this tutorial is to offer an overview of these interactions and quantify the reliability impact of the new features. Particularly, the tutorial will emphasize the role of sidewall crystal orientation, fin corner effects, the effects of self-heat dissipation, and vertical junctions. Beginning with a discussion of the transistor design, physics, and performance, the tutorial will then describe how tri-gate features can improve reliability over planar technologies. Finally, traditional transistor reliability mechanisms such as TDDB, BTI, Hot Carrier, SILC, SER, ESD, and body-bias will be reviewed in the context of tri-gate influences.
After receiving his PhD in Electrical Engineering from Purdue University, West Lafayette, IN, in 2005, Anisur Rahman joined the 65nm CMOS Process Technology development team at Intel Corporation as a Transistor Quality and Reliability Engineer. Since then, as core member of 32nm, 22nm and finally 10nm High-K/MG CMOS technology development teams for CPU and SoC applications, he lead the efforts to define and shape Intel’s transistor architectures, and process flow optimizations to intercept full-chip quality and reliability specifications.
During this period his responsibilities encompassed: guide FEOL process development activities by incrementally solving the multi-dimensional technology optimization problem satisfying performance, yield, and reliability constraints; develop transistor level Fail Mode Effect Analysis (FMEA) tools; deliver reliability model for conventional fail mechanisms, e.g., BTI, HotC, and TDDB; pre-silicon reliability assessments and post-silicon product qualification tests.
Dr. Rahman’s current research interests has been widened to include: conventional transistor fail mechanism in deeply scaled CMOS technology; device level noise, especially RTN, characterization, modeling, mitigation through process optimization and exploration of RTN’s role in temporal fluctuations in SRAM, a.k.a. erratic-bits; variation aware circuit design to ensure optimum reliability and yield; full-chip performance guard-banding against end-of-life aging loss by projecting individual transistor reliability models to circuit aging and finally mapping to EOL product performance loss.
Dr. Rahman authored/co-authored 40+ peer reviewed publications in international conferences and journals, and has be awarded five patents. He serves in the technical and management committees of IEDM and IRPS conferences and as a reviewer for electron devices, solid-state electronics, applied physics, and microelectronics journals.
In Hak Baick
Optimal Design Rule and Reliability of Chip-to-Package Interaction.
Chip-to-package interaction (CPI) related failures have increased and diversified due to adoption of heterogeneous integrations, large/thick Si die and micro-unit embedded BEOL structures (i.e., MIMCAP and MRAM). The CPI failure can occur in various modes (i.e., BEOL delamination, Si interposer cracks and passivation cracks) depending on the integrations and package types. Consequently, suitable design rules and micro-architecture targeting package types are necessary, and reliability efforts are being made to distinguish between the vital from the needless factors regarding BEOL stacking design, bump dimension, TSV/MIMCAP positioning and material properties. This talk will cover CPI activities on enhancing package level reliability followed by optimal designs along BEOL to a given package type. Also, the time-dependent material property and its effects on the package level reliability will be discussed.
In Hak Baick has worked on 28nm/14nm/10nm Chip-to-Package Interaction (CPI) at Technology Q&R group in System LSI Business of Samsung Electronics since 2014. In addition to ultra low-k dielectric material for advanced interconnects, his research work included CPI reliability of organic/Si interposer devices, TSV, MIMCAP, MRAM and 7nm BEOL and packages. Recently, his research focus on MIMCAP reliability and package material properties were presented at IRPS (2015) and ECTC (2016), respectively. Dr. In Hak earned his Ph.D. degrees (2013) in Chemical Engineering from the University of Maryland focusing organic material’s characterization, modeling & simulation of time-dependent phenomena and material reliability.