SiC MOSFET Reliability Issues and Implications for Qualification Testing
There are a number of potential reliability issues associated with SiC power MOSFETs, including threshold-voltage stability, gate-oxide reliability, body-diode robustness, short-circuit current robustness, and radiation effects. This talk is primarily focused on threshold-voltage stability and the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold-voltage stability is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct-tunneling mechanism in response to changes in gate bias. This time dependence is not properly accounted for in the existing test methods for assessing high-temperature gate-bias (HTGB) effects, which allow temporary removal of bias during cool down and significant un-biased delay (up to 96 hours) before the post-stress measurements are performed. However, this delay, introduced to accommodate the practical constraints of industrial testing, renders this test practically meaningless due to the significant recovery that occurs in the charge states of the near-interfacial oxide traps. This difficulty can be overcome by reapplying the gate bias for a brief period of time before measuring. Details of the nature of the near-interfacial oxide traps will be discussed, including their activation energy. All this work will be presented within the context of standards development within JEDEC, and a new SiC power-devices qualification working group.
Dr. Aivars Lelis, who received his Ph. D. in Reliability Engineering from the University of Maryland in 2011 and his M.S. degree in Electrical Engineering from the Johns Hopkins University in 2000, leads the Wide Bandgap Device Reliability Team of the Power Conditioning Branch at the U.S. Army Research Laboratory in Adelphi, MD, with a focus on the device reliability physics of SiC and GaN MIS-based power devices, for high-temperature, high-efficiency power conversion and conditioning for advanced Army systems.
Kong Boon Yeap
Realistic model of BEOL and MOL TDDB
In this study, the BEOL and MOL TDDB failure rate integration method is developed and verified, using: (a) long term package level tests on test structures for each failure mode; and (b) circuit level tests on SRAM and logic cells. The failure rate integration method determines the product realistic failure rate based on high volume manufacturing data. We will further demonstrate that product realistic failure rate has little to no impact from changing the voltage acceleration models, as long as the spacing variation is the dominant factor in the product failure rate.
Kong Boon Yeap received the Ph.D. degree in mechanics of materials from the National University of Singapore, Singapore, in 2009. He was a Post-Doctoral Researcher with the Fraunhofer Institute, Munich, Germany, with expertise in the field of nanomechanics, materials science, and reliability of semiconductor research. He is currently with GLOBALFOUNDRIES, Malta, NY, USA, as a Reliability Engineer, focusing on time-dependent dielectrics breakdown of back-end-of-line and middle of line, and circuit level reliability. He has published more than 50 technical papers in international journals and conference proceedings, in the area of material science and reliability engineering.
Reliability of FinFET Devices
Tri-gate transistor architecture represents a radical departure from that of traditional planar transistors. Due to the 3D features associated with their vertical narrow fin, the tri-gate transistor can interact with traditional reliability mechanisms in new ways. The goal of this tutorial is to offer an overview of these interactions and quantify the reliability impact of the new features. Particularly, the tutorial will emphasize the role of sidewall crystal orientation, fin corner effects, the effects of self-heat dissipation, and vertical junctions. Beginning with a discussion of the transistor design, physics, and performance, the tutorial will then describe how tri-gate features can improve reliability over planar technologies. Finally, traditional transistor reliability mechanisms such as TDDB, BTI, Hot Carrier, SILC, SER, ESD, and body-bias will be reviewed in the context of tri-gate influences.
After receiving his PhD in Electrical Engineering from Purdue University, West Lafayette, IN, in 2005, Anisur Rahman joined the 65nm CMOS Process Technology development team at Intel Corporation as a Transistor Quality and Reliability Engineer. Since then, as core member of 32nm, 22nm and finally 10nm High-K/MG CMOS technology development teams for CPU and SoC applications, he lead the efforts to define and shape Intel’s transistor architectures, and process flow optimizations to intercept full-chip quality and reliability specifications.
During this period his responsibilities encompassed: guide FEOL process development activities by incrementally solving the multi-dimensional technology optimization problem satisfying performance, yield, and reliability constraints; develop transistor level Fail Mode Effect Analysis (FMEA) tools; deliver reliability model for conventional fail mechanisms, e.g., BTI, HotC, and TDDB; pre-silicon reliability assessments and post-silicon product qualification tests.
Dr. Rahman’s current research interests has been widened to include: conventional transistor fail mechanism in deeply scaled CMOS technology; device level noise, especially RTN, characterization, modeling, mitigation through process optimization and exploration of RTN’s role in temporal fluctuations in SRAM, a.k.a. erratic-bits; variation aware circuit design to ensure optimum reliability and yield; full-chip performance guard-banding against end-of-life aging loss by projecting individual transistor reliability models to circuit aging and finally mapping to EOL product performance loss.
Dr. Rahman authored/co-authored 40+ peer reviewed publications in international conferences and journals, and has be awarded five patents. He serves in the technical and management committees of IEDM and IRPS conferences and as a reviewer for electron devices, solid-state electronics, applied physics, and microelectronics journals.
In Hak Baick
Optimal Design Rule and Reliability of Chip-to-Package Interaction.
Chip-to-package interaction (CPI) related failures have increased and diversified due to adoption of heterogeneous integrations, large/thick Si die and micro-unit embedded BEOL structures (i.e., MIMCAP and MRAM). The CPI failure can occur in various modes (i.e., BEOL delamination, Si interposer cracks and passivation cracks) depending on the integrations and package types. Consequently, suitable design rules and micro-architecture targeting package types are necessary, and reliability efforts are being made to distinguish between the vital from the needless factors regarding BEOL stacking design, bump dimension, TSV/MIMCAP positioning and material properties. This talk will cover CPI activities on enhancing package level reliability followed by optimal designs along BEOL to a given package type. Also, the time-dependent material property and its effects on the package level reliability will be discussed.
In Hak Baick has worked on 28nm/14nm/10nm Chip-to-Package Interaction (CPI) at Technology Q&R group in System LSI Business of Samsung Electronics since 2014. In addition to ultra low-k dielectric material for advanced interconnects, his research work included CPI reliability of organic/Si interposer devices, TSV, MIMCAP, MRAM and 7nm BEOL and packages. Recently, his research focus on MIMCAP reliability and package material properties were presented at IRPS (2015) and ECTC (2016), respectively. Dr. In Hak earned his Ph.D. degrees (2013) in Chemical Engineering from the University of Maryland focusing organic material’s characterization, modeling & simulation of time-dependent phenomena and material reliability.
Reliability Aspects of Novel Anti-ferroelectric Non-volatile Memories compared to Hafnia based Ferroelectric Memories
The discovery of the ferroelectric (FE) properties within HfO2 bridged the scaling gap between state-of-the-art technology nodes and ferroelectric memories. However, beside non-volatility, new memory concepts have to ensure sufficient endurance and operation stability. Recently, it was shown [Pešić et al. IEDM 2016] that anti-ferroelectric (AFE) materials exhibit very stable and much higher endurance with respect to the FE counterparts, which exhibit changes in the memory window (MW) followed by either hard breakdown or closure of MW much earlier than desired.
Motivated by remarkable performance of AFE, we analyze physical mechanisms behind this high endurance strength. By characterizing the pure film properties in capacitor stacks and switching performance when integrated into devices, we compare the underlying mechanism and investigate the root cause for degradation of both FE and AFE memories. Combining the switching dynamics experiments, charge trapping and charge pumping tests as well as the defect spectroscopy with comprehensive modeling, we analyze if the lower energetic barrier to be overcome together with partial switching is responsible for the higher endurance and phase stability of AFE with respect to the FE based memories.
Milan Pešić received the M.Sc. in Nanoelectronics systems at the Technical University of Dresden, Germany. Since 2014, he has been pursuing the Ph.D. degree in the Nanoelectronic Materials Laboratory NaMLab gGmbH and at Technical University of Dresden, Germany. Currently he holds a position of Scientist at NaMLab. His research activities are in the field of non-volatile memories. Particularly, his interests are the oxide reliability, ferroelectrics, characterization and modeling of emerging non-volatile memories as well as the energy efficient electronics (steep-slope device). He authored/coauthored 20+ publications.
Reliability-performance evaluation for scaled multi-materials device stacks
We review our recent works aimed at the physical understanding of trap-related and breakdown phenomena limiting the performance and the high-field reliability of GaN HEMTs. We specifically focus on cases in which combining experiments with numerical device simulations has been the key for attaining a deeper physical insight into the experimental observations. HEMT technologies under study are both Schottky- and insulated-gate HEMTs for either RF and switching power applications. Investigated phenomena include trap-related effects, RF power gain collapse, threshold-voltage instabilities, high-electric-field degradation, lateral and vertical breakdown.
Giovanni Verzellesi was born in Italy in 1964. He received the “Laurea” degree in Electrical Engineering from the University of Bologna, Bologna, Italy, in 1989, and the Ph.D. degree also in Electrical Engineering from the University of Padova, Padova, Italy, in 1994.
He was with the University of Trento, Trento, Italy, as a Research Associate of electronics from 1994 to 1999. In 2000 he joined the University of Modena and Reggio Emilia, Italy, where he became Associate Professor in 2001 and full Professor of electronics in 2006.
His research activity has been concerned with the modeling and characterization of semiconductor devices and sensors and it currently focuses on III-V-based field-effect transistors and gallium-nitride LEDs. He has coauthored about 200 papers in international journals and proceedings of international conferences.
Dr. Verzellesi is a Senior Member of the IEEE. He has served in the technical program committee of the following conferences: IEEE IEDM, IEEE IRPS, ESSDERC, ESREF, EXMATEC, HETECH.
Compact modeling for reliability simulation
IC reliability is an ever-growing concern due to the increasing electric fields associated with technology down-scaling. As a consequence, the task of guaranteeing IC reliability is gradually shifting from device to the circuit-design level . IC reliability simulation tools  are very helpful for achieving this, and are provided by all major EDA vendors today. In IC reliability simulation, the traditionally separate fields of reliability characterization and compact modeling are coming together. This introduces some specific problems which will be addressed in this paper.
Andries Scholten received the M.Sc. and Ph.D. degrees in experimental physics from Utrecht University, The Netherlands, in 1991 and 1995, respectively. In 1996, he joined Philips Research Laboratories (now NXP Semiconductors), Eindhoven, The Netherlands, where he has worked on compact MOS modeling for circuit simulation, with a focus on the modelling of thermal noise and non-quasi-static effects.
He has contributed to the development and industrialization of well-known compact MOSFET models such as MOS Model 9, MOS Model 11, and the world-standard PSP model. His current research is directed towards RF CMOS and HBT reliability and reliability simulation.
Accurate prediction of device reliability from fundamental properties of point defects in dielectric stacks
Point defects, such as vacancies and interstitials together with strained bonds in the bulk and interface, of dielectric films affect the electrical characteristics of devices by controlling the charge transport and trapping of charge carriers in devices incorporating these dielectrics. Changes in the density of these defects or to their trapping characteristics due to electrical stress and temperature are the major cause of reliability issues in integrated circuits. A physics based multiscalar simulation approach is described that can accurately simultaneously predict both the performance and the reliability of devices, using the same microscopic description of the electronic properties of the defects and mechanisms of charge transport. Simulated electrical characteristics are compared to experimental data for single layer and multilayer dielectric stacks in capacitors and transistors. The dielectrics span from Silicon Dioxide to Aluminum Oxide to high k dielectrics such as ZrO2, HfO2 and TiO2. With a minimal set of physical parameters, a good fit to measured I-V curves is obtained over the entire voltage range from low voltages to breakdown, and over a wide temperature range. Using these same parameters, simulated time to breakdown distributions of different dielectric materials stacks as a function of electrical tress and temperature are calculated and are shown to be in good agreement with experimental distributions. The advantage of the simulator is that it extrapolates operational lifetimes from accelerated tests more accurately than standard phenomenological equations. In the case of SiO2, a more detailed model of charge trapping at precursor sites, followed by field induced breakage predicts the more complex dependence on electric field than previously published models. As a measure of self-consistency of the physical approach , the PBTI for a high k metal gate stack is reproduced using the same defect distribution obtained from fitting the Ig-Vg curves.
Dipu Pramanik is currently CEO and Co-founder of MDLSoft Inc, which has built an innovative platform to intimately link materials and devices. He received a PhD in Physics/Materials Science from Cornell and has worked in semiconductor industry for the last 35 years. Over the course of 13 years at VLSI Technology he contributed to all the major areas needed for the development and production of ASIC chips, including process integration, device integration, reliability and packaging. As Director of Process Technology at VLSI Technology he was responsible for the development of leading edge logic processes from inception all the way to high volume production. He subsequently moved into design technology to lead the effort in incorporating DFM methodology into the chip design flow and to integrate RF and Analog circuits with digital blocks for wireless chips. He founded Virtual Wireless, to design wireless baseband chips for the 3G market. Later he joined Synopsys and as head of TCAD grew the business unit several-fold and made it the dominant player in this area. From Synopsys he moved to Cadence where he was VP of DFM at Cadence. He returned to his roots in materials/devices at Intermolecular Inc where as VP/Fellow of core technology, he pioneered a workflow that coupled ab-initio and multiscale simulations with materials databases to complement combinatorial experiments. This was used successfully to identify materials solutions for a wide range of industrial applications in semiconductors, displays, clean energy.
Negative Capacitance Transistors
Phase transition materials have long been investigated for fundamental physics and also for potential application in electronics. In this presentation, I shall discuss how a controlled phase transition can lead to fundamentally new switching devices that has significantly less energy dissipation compared to the state of the art. In particular, I shall talk about the state of negative capacitance that can be achieved in certain material systems with stored energy of phase transition. Our recent experiments with ferroelectric materials have shown that such a state of negative capacitance can actually be achieved. I shall also describe our very recent results where such negative capacitance, when combined with conventional transistors, lead to effects that was long believed to be impossible. Finally, I shall discuss how these effects can usher in a new era of energy efficient electronics.
S. Salahuddin is an associate professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. His work has focused mostly on conceptualization and exploration of novel device physics for low power electronic and spintronic devices. Salahuddin has received the Presidential Early Career Award for Scientist and Engineers (PECASE), the highest honor bestowed by the US Government on early career scientist and engineers. Salahuddin also received a number of other awards including the NSF CAREER award, the IEEE Nanotechnology Early Career Award, the Young Investigator Awards from the Air Force Office of Scientific Research (AFOSR) and the Army Research Office (ARO) and best paper awards from IEEE Transactions on VLSI Systems and from the VLSI-TSA conference. In 2012, Applied Physics Letters (APL) highlighted two of his papers among 50 most notable papers among all areas published in APL within 2009-2012. Device simulation codes developed at Salahuddin’s Lab is used by major semiconductor industries. At Berkeley, Salahuddin is a co-director of the Berkeley Device Modeling Center and Berkeley Center for Negative Capacitance Transistors. He is on the editorial board of IEEE Electron Devices Letters and currently chairs the IEEE Electron Devices Society committee on Nanotechnology.
HfO2-based RRAM: Integration Possibilities and Variability Study
Resistive random access memories (RRAM) based on transition metal oxides are considered as promising emerging non-volatile memories, due to their simple and scalable structure. However their variability and cycling understanding remain a major roadblock. In this presentation, we will mainly focus on HfO2-based RRAM. The different integration approaches and typical performances will be reviewed for this specific system. Then a comparison with respect to other emerging technologies will be provided. Finally, the variability of OxRAM will be discussed based on a multi-kbit array study.
Dr. Laurent Grenouillet received the Engineer degree in physics in 1998 from the National Institute of Applied Sciences (INSA) in Lyon, France, and the PhD degree in electronic devices in 2001. After a post-doctoral position in the field of Molecular Beam Epitaxy, he joined CEA-Leti in 2002 and worked on GaAs-based VCSELs emitting in the 1.1-1.3μm range and single photon sources with quantum dots. In 2006, he joined the Silicon Photonics group where he developed CMOS compatible hybrid III-V on silicon lasers. In 2009, he joined IBM Alliance in Albany as a Leti assignee to contribute to the development of FDSOI technology. Within Albany state-of-the-art facilities, he extensively worked on device integration to improve performance of FDSOI devices (28nm and 14nm node). Back in France at CEA-LETI in 2013, he focused on the performance boosters for the 10nm node FDSOI technology, and took part to the FDSOI technology transfer to Global Foundries (22FDX) in 2015. During that period he joined the Memory Laboratory to explore OxRAM memories. Laurent Grenouillet authored or co-authored over 80 papers (conferences and journals) and has filed over 35 patents.
2D vs 3D NAND Technology: A Reliability Benchmark
The reliability performance degradation of ultra-scaled (1x node) 2D NAND memories has been one of the key limitations of further 2D NAND scaling, together with increased process complexity. To this regard, the 3D NAND technology provides several advantages to enable improved cell reliability characteristics.
First, the cell capacitance increases due to bigger cell size, allowing for storing more electrons for a given threshold voltage (Vt) change and strongly reducing the cell sensitivity to few electron fluctuations phenomena. Second, the cell to cell interference is strongly reduced, since the bitline-to-bitline component (typically the highest in a 2D technology) is completely eliminated. Both these characteristics lead to a much tighter Vt distributions after placement (for a given program step) with respect to the last 2D NAND generation. Moreover, the gate all-around structure dramatically increases the channel boosting capability during the inhibit operation and provides good immunity against program disturb, as long as the mechanisms related to high channel potential (like hot-e injection) are managed appropriately. All these characteristics, together with the proven reliability of a conventional FG memory cell (chosen to develop our 3D NAND products) allow for good enough post-cycling performance to enable 3bit/cell (TLC) technology for enterprise applications.
We faced two main reliability challenges developing our 3D FG NAND technology.
The first one is related to the conduction properties of the polysilicon channel. The polysilicon grain boundaries introduce a (partially) percolative conduction mechanism, impacting the array read operation, since they act as energy barriers for electrons traveling from source to drain during cell Vt sensing. Therefore, 3D NAND memories exhibit a stronger temperature dependence of both string current and Vt-instabilities (mainly RTN related) with respect to 2D NAND. To manage the Vt placement degradation related to these mechanisms, a proper program window allocation and an accurate temperature compensation strategy are required in order to guarantee End-of-Life reliability performance.
The other one is related to the erase operation. The architectural choice of CMOS Under the Array (CuA) does not allow to bias the channel directly to the erase voltage (Verase). Instead, Verase is applied to the source contact and it is passed to the channel through GIDL generation at the outer junction of the Select Gate (SG). This technique can potentially cause higher erase performance variation (due to string to string GIDL differences) and degraded SG Vt uniformity (due to the SG high bias requirement). However, a fine optimization of the Verase and SG waveforms has been proven to guarantee excellent uniformity and reliability of the erase operation and a very stable SG Vt over cycling.
Giuseppina Puzzilli received her MS and PhD in Electronic Engineering in 2003 and 2007 respectively, from University of Rome “La Sapienza”. In 2008 she joined Micron-MTI where she currently leads the NAND Cell Reliability Team. Her work is mainly focused on the interaction between NAND component and SSD system from performance and reliability standpoint.