The role of defects on reliability aspects in GaN power devices
Gallium nitride (GaN) offers fundamental advantages over silicon. In particular the higher critical electrical field makes it very attractive for power semiconductor devices with outstanding specific dynamic on-state resistance and smaller capacitances compared to silicon switches, which makes GaN HEMTs great for high speed switching.
However, defects in GaN epitaxial layers grown on silicon substrate have been a long standing topic going hand-in-hand with the understanding of reliability aspects of such devices. This talk summarizes the current understanding of the most relevant defects in GaN power HEMTs:
Interface defects controlling the electron concentration in the device channel, the lateral 2-dimensional electron gas, and buffer defects required to establish a vertically insulating GaN buffer. The latter is typically achieved by introducing Carbon atoms during the buffer growth acting dominantly as acceptor-like defect states. Finally, some of the roles that these defects on reliability and device aspects will be discussed.
Clemens Ostermaier has received his master’s degree in semiconductor engineering from Kyungpook National University in Daegu/South Korea in 2008 and his Ph.D. degree in electrical engineering from Vienna University of Technology in 2011, where he a graduated with promotio sub auspiciis, the highest possible honor in education in Austria. He joined Infineon Technologies Austria in 2010 as part of the development team of GaN power devices with special interest and passion on the technology, design and reliability aspects of such devices. Since 2019 he is also working as a university lecturer at the Vienna University of Technology. He has supervised several PhD and master students and authored and co-authored over 30 peer-reviewed scientific journal publications, more than 50 conference contributions and over 20 international patent and patent applications in the ﬁeld of power semiconductors.
Electromigration (EM) drastically decreases the reliability of electronic interconnects, as it leads to voiding of metal lines. In order to mitigate or inhibit electromigration failures, it is of foremost importance to understand the mechanisms by which they occur. Therefore, a reliable and relatively fast test method is required. Because under operation conditions it might take years before EM failures happen, the presently used, standard electromigration test methods are based on accelerated testing. In order to then extrapolate the observed lifetimes to real use conditions, Black’s law, which was discovered in the late 1960’s for aluminum lines , is used. Its application to modern-day interconnects, however, is becoming increasingly more questionable and often can no longer provide the required understanding that the semiconductor industry is seeking to continue scaling while meeting reliability specs . Moreover, these accelerated EM tests are time-consuming and destructive.
In this talk we discuss a new EM test methodology, based on low-frequency noise (LFN) measurements and validate it by both experiments and theoretical modeling.
The main advantages of the low-frequency noise methodology over the standard accelerated EM tests are that it is non-destructive, much faster, closer to operation conditions and provides more fundamental understanding.
We show the application of LFN measurements to investigate EM mechanisms in scaled interconnects. Cu grain boundary diffusion was identified as the prime concern for EM reliability in lines of sub 30nm ½ pitch.
Furthermore, at line-widths below 20nm, Cu will have to be replaced by alternative metals due to its unacceptable resistivity increase  and insufficient electromigration performance . Potential candidates are cobalt, ruthenium and tungsten. In this talk we show how the LFN measurements can be used to study their EM activation energy.
 Black, J. R. Electromigration—A brief survey and some recent results. IEEE Transactions on Electron Devices, 16, 4 (1969), 338–347.
 Lloyd, J. Black’s law revisited—Nucleation and growth in electromigration failure. Microelectronics Reliability 47, 9-11 (sep 2007), 1468–1472.
 Kapur, P., McVittie, J. P., and Saraswat, K. C. Technology and reliability constrained future copper interconnects. I. Resistance modeling. IEEE Transactions on Electron Devices, 49, 4 (2002), 590–597.
 Kapur, P., Chandra, G., McVittie, J., and Saraswat, K. Technology and reliability constrained future copper interconnects. II. Performance implications. IEEE Transactions on Electron Devices 49, 4 (apr 2002), 598–604.
Sofie Beyne is a PhD student at imec and KU Leuven, researching electromigration in nano-interconnects. For this work she was granted a scholarship by the fund for scientific research in Flanders (FWO). In 2015 she received a master’s degree in materials science and engineering from KU Leuven, which included a one-year exchange at EPFL in Switzerland. She has authored and co-authored several peer-reviewed scientific journal publications and conference papers.
Frequency-Modulated Charge Pumping for Highly Leaky MOS Devices
Charge pumping (CP) is one of the most relied upon techniques used to quantify interface defects in metal-oxide-semiconductor devices. However, conventional charge pumping is easily hindered by excessive gate leakage currents which render the technique unsuitable for advanced technology nodes. This presentation will discuss the so-called frequency-modulated charge pumping methodology, in which conventional quasi-dc charge pumping is transformed into a true ac measurement. The ac detection scheme is highly resistant to gate leakage currents and extends the usefulness of charge pumping as a defect monitoring tool for future technologies. The topics covered include (1) a basic physical understanding and measurement techniques for conventional CP, (2) measurement challenges associated with excessive leakage current and the failure of conventional methods, (3) physical basis for leakage immunity and experimental methods for implementing simple frequency-modulated CP, and (4) examples using highly leaky technologies and applications relevant to reliability monitoring
Dr. Ryan is an electrical engineer and leader of the Magnetic Resonance Spectroscopy Project in the Alternative Computing Group of the Nanoscale Device Characterization Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). He received the B.S. degree in Physics from Millersville University, Millersville, PA in 2004. He received the M.S. degree in Engineering Science and the Ph.D. in Materials Science and Engineering from The Pennsylvania State University, University Park, PA in 2006 and 2010, respectively. In 2010, he was awarded a National Research Council post-doctoral fellowship which he spent at NIST where he is currently employed as a staff member and project leader. He has been involved in the technical and managerial committees of both the IEEE IRPS and IEEE IIRW conferences, having served as the general chair of the IIRW in 2015.
Barry J. O’Sullivan
Reliability engineering enabling continued logic for memory device scaling
Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-κ metal-gate (HKMG) stacks into the logic and high-voltage (e.g. I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong lifetime degradation is observed as soon as high-k layers are deposited on top of the thick interfacial layer. The NBTI degradation is correlated to a diffusion of Ti/Hf (potentially Al) elements from the HKMG gate stack down to the interfacial layer. Potential solutions for this reliability challenges will be reported. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high-κ fluorination and/or cap, metal gate) will be presented. Potential solutions for the reliability challenges of high-κ metal gate (HKMG) integration into DRAM high-voltage peripheral logic devices are reported.
Barry J. O’Sullivan received the B.Sc. degree in Applied Physics from University of Limerick, Ireland in 1998. He received the M.Eng.Sc. and Ph.D. degrees (Microelectronics), from the Tyndall Institute, Cork, Ireland, for studies characterizing defects at the silicon/dielectric interface, in 2000 and 2004, respectively. Since then, he has been at IMEC, Leuven, Belgium, initially quantifying defects and reliability of advanced gate stacks for the 45 nm and 32 nm CMOS technology nodes. From 2009-2016 he worked on high efficiency silicon solar cell design, fabrication and characterisation, while his current research focus includes reliability characterization for advanced logic and memory applications.
Defect Spectroscopy in MOS Transistors
Modern transistors fabricated employing silicon wafers have been scaled down to dimensions in the nanometer regime. Despite the advantage of an increased switching rate and a larger number of devices per unit area, severe reliability issues have to be tackled in these devices. The most prominent reliability issue which degrades the device performance is know as the bias temperature instability (BTI). BTI manifests itself as a threshold voltage drift and its characterization and modeling has received much attention during the last decades. For instance (stress) IDVG, CV or DCIV measurements, but also measure-stress-measure (MSM) schemes are typically used. However, mostly large area devices have been investigated in that regard, with the drawback that only the average response of many defects can be studied. This enables only the application of mostly empirical models to explain the intricate behavior of charge trapping. Conversely, by probing nanoscale transistors, single charge transition events of individual traps can be assessed. This enables a microscopic zoom mechanism and allows a detailed study of the charge trapping kinetics and physics of single defects. To probe single defects at a great level of detail the time-dependent defects spectroscopy (TDDS) has been proposed. In order to model the charge trapping kinetics, an advanced defect model has been developed around the non-radiative multiphonon (NMP) theory.
Michael Waltl received the PhD degree in electrical engineering from the TU Wien, Austria, and is currently employed as Senior Scientist at the Institute for Microelectronics at the TU Wien. As part of his scientific work in recent years on bias temperature instability in nanoscale transistors he was put in charge of the development of defect probing characterization environments. Currently, Dr. Waltl is the director of the Christian Doppler Laboratory for Single-Defect Spectroscopy in Semiconductor Devices and is responsible for the device characterization laboratory at the Institute for Microelectronics. His scientific focus is put on experimental characterization and modeling of performance degradation issues prevalent in semiconductor devices and devices with more exotic 2D materials. He received the best paper award at IRPS 2014, has been involved in the technical committee of the ESREF 2014, has co-supervised several PhD, master and bachelor students and authored and co-authored over 20 peer-reviewed scientific journal publications, and more than 30 conference contributions.