Fallen Leaf Lake

Invited Speakers

Ernest Wu

IBM

Fundamental limitations of existing models and future solutions for dielectric breakdown and RRAM applications

Two important engines lie at the heart of dielectric reliability assessment and prediction methodologies: a statistical distribution model and a field/voltage acceleration model for data parameter extraction and reliability projection. Over last fifty years, the Weibull/ Poisson model and constant field-acceleration exponential model have been proven to be useful for more-or-less ideal situations. However new applications and experimental findings have challenged and exposed the fundamental limitations of these decades-old models. The time-dependent clustering model and power-law field/voltage models have emerged to meet these new challenges in a wide range of applications from dielectric breakdown (BD) statistics in BEOL/ MOL/FEOL cases to Reset/Set statistics of RRAM operations. Recent advances in atomistic simulation and microscopic modeling provide fresh insights for the correct choice of field/voltage acceleration models. In this talk, we will combine the rigorous experimental results justified from the statistical principles with the state-of-art atomistic modelling work to demonstrate these promising solutions for qualification and modelling of dielectric breakdown in CMOS advanced technology nodes and forming process of filamentary resistive memory applications.

Dr. Ernest Y. Wu is a senior technical staff member at IBM Research Division and has been responsible for technology qualification and development of dielectric reliability methodologies since 1995 for many generations of CMOS technologies from 250nm down to 7nm nodes including SiO2, high-k, and low-k dielectrics across FEOL/MOL/BEOL applications with more than 150 papers, numerous invited talks and tutorials in international conferences and Journals including 15 IEDM papers as the leader author. In 2004, he received an IBM Outstanding Technical Achievement Award for the original development work on power-law acceleration model of FEOL gate dielectrics which has been widely used for technology qualification. In 2016, he received an IBM outstanding technical award for statistics and physics of transistor breakdown. He is an IEEE Fellow and his research interests include statistics, device physics and simulation, dielectric reliability physics and its applications to assessment of product/circuit failures

Stewart Rauch

GLOBALFOUNDRIES

Considerations for Hot Carrier Modeling in CMOS RF Applications

The CMOS hot carrier modeling legacy within IBM has concentrated on digital applications. Within GlobalFoundries, the advent of a growing RF CMOS market has led us to re-evaluate many aspects of this methodology. Our progress to date and ongoing plans for RF hot carrier modeling are reported. The main items are: (1) Implications of an increased importance of low vGS regimes of operation for both stress and measurement dependence of hot carrier shift, (2) Methods for the accurate modelling of the shift of the analog/RF key parameters of gm and gds, (3) Potential impacts of Cgs and Cgd shifts, and (4) Validity of the quasi-static approximation at high frequencies.

Stewart Rauch is currently a Principal Member of Technical Staff at GlobalFoundries, NY, working in the areas of reliability of Si photonics and RF CMOS. Formerly he was a faculty member at State University of New York, New Paltz, and a Senior Technical Staff Member at IBM Semiconductor Research and Development Center (NY), specializing in hot carrier, bias temperature instability, and soft error reliability of state of the art CMOS technologies. He is a Senior Member of IEEE, a Life Member and Distinguished Lecturer of the Electron Devices Society, and frequent journal reviewer for such publications as the IEEE Transactions on Electron Devices and the Microelectronics Reliability journals, etc.

 

Pragya Shrestha

National Institute of Standards and Technology

Reliable and Accurate Electrical Characterization of RRAM Devices/materials

Resistive memory (RRAM) has been studied a lot with various materials and structures (1R-1R, 1T-1R, 1R etc). Variability has been identified as a major set-back for these devices. So, the race has been to understand the source of variability and minimize it. But novel devices are not always easy to characterize. They come with their set of issues that may not be accurately probed using conventional CMOS characterization tools. As for RRAM devices they are very sensitive to the energy (current and the time). Therefore, the information may be plagued with artifacts due to the setup being used. A lot of work has been done to characterize the switching of these devices but the studies do not share the same setup. So, the question is how should numerous studies be compared when the measurement itself may be the source of variation and What would be the best way to perform the electrical characterization such that the information is accurate and easily comparable to any another RRAM device/material? We will discuss these issues and talk about the solutions and their upshots.

Pragya Shrestha received performed her Ph. D. Research at National Institute of Standards and Technology (NIST) on electrical characterization of RRAM and received her Ph.D. from Old Dominion University, Virginia. She is now a Research Scientist at Theiss Research working at NIST.

Gerhard Rzepa

TU Wien

Extraction of defect band properties

Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research, the defect structures and the generation mechanisms are not fully understood. Most light has been shed onto the charging mechanisms of pre-existing oxide defects by using the non-radiative multi-phonon theory. Here, we present how the gist of physical models for pre-existing oxide defects can be efficiently abstracted at a minimal loss of physical foundation and accuracy. Together with a semi-empirical model for the generation and transformation of defects, we establish a reaction-limited framework for unified simulation of bias temperature instabilities (BTI). The applications of the framework we present here cover simulation of BTI for negative (NBTI) and positive (PBTI) gate voltages, lifetime extrapolation, AC stress with arbitrary signals and duty cycles, and gate stack engineering.

Gerhard Rzepa received a BSc degree in Electrical Engineering in 2010 and a Diplomingenieur degree in Microelectronics in 2013, both from the TU Wien (Vienna University of Technology). In 2018 he finished his PhD studies on the topic of modeling of bias temperature instabilities at the Institute for Microelectronics, TU Wien, and obtained his doctoral degree. He continues to work at the Institute for Microelectronics where he focuses on the research of oxide degradation, device variability and measuring and modeling of related reliability phenomena such as bias temperature instabilities, hot carrier degradation, random telegraph noise, and stress-induced leakage currents.

Prof. Dr. Edmundo A. Gutiérrez-D.

Department of Electronics of the National Institute of Astrophysics, Optics and Electronics (INAOE) in Puebla, Mexico

RF/DC reliability and random telegraph noise under the influence of a magnetic field on CMOS advanced technologies

Experimental results on 28 GHz reliability and random telegraph noise of a 45nm SOI technology, are introduced. In order to have an insight into the physics of degradation and reliability, an external magnetic field is applied. A general observation is that reliability is frequency dependent (in the 10 MHz-67GHz frequency range), that an external magnetic field changes the capture/emission at the interface traps altering the degradation mechanism. Another relevant experimental observation is that degradation reduces at high frequencies at under specific levels of degradation. A hypothetical theory is introduced in order to explain the magneto-modulation of trapping/detrapping and reduction of degradation at high frequencies.

 

Prof Gutiérrez-D. received his PhD from the Catholic University of Leuven (KUL), Belgium in 1993, with the thesis entitled “Electrical performance of submicron CMOS technologies from 300 K down to 4.2K”. From 1988 to 1993 was a research assistant at the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. In 1993 joined as a researcher the Department of Electronics of INAOE. In 1996 spent one year as invited Professor at the Simon Fraser University in Vancouver, Canada. In 1996 he also spent two months at the University of Sao Paulo, Brazil as a Summer PhD lecturer. From 1999 to 2000 was appointed Head of the INAOE Department of Electronics. From 2000 to 2002 spent two years as Design Manager of the Motorola Mexico Center for Semiconductor Technology in Puebla City. In 2002 he was also invited Professor at the Technical University of Vienna, Austria. From 2002 to 2005 rejoined INAOE as Professor of the Department of Electronics. From 2005 to 2007 was the Research Manager of the Intel Systems Research Center Mexico in Guadalajara City.

Prof. Gutiérrez is author of the books “Low Temperature Electronics, Physics, Devices, Circuits and Applications” (Academic Press, 2000), and “Nano-Scaled Semiconductor Devices, Physics, Modelling, Characterisation, and Societal Impact”, IET Press, 2016. He has supervised 7 M.Sc. and 13 PhD theses, and has published more than 120 scientific papers and conferences in the field of physics of semiconductor materials and devices, including MOS transistors, temperature, optical, and magnetic sensors.

Prof. Gutiérrez-D. is Associate Editor of Electron Device Letters.

Currently Prof. Gutierrez is with the Department of Electronics of the National Institute of Astrophysics, Optics and Electronics (INAOE) in Puebla, Mexico. Prof. Gutiérrez is member of different Review Committees of the Mexico National Council of Science and Technology (CONACyT), and Senior Member of the IEEE organization.

 

Daniel J Lichtenwalner

Wolfspeed, Inc (a Cree company)

Studies of SiC MOSFET Reliability under High Gate and Drain Fields

Daniel J. Lichtenwalner received his PhD degree in Materials Science from the Massachusetts Institute of Technology in 1990, under David A. Rudman and Alfredo C. Anderson, in the area of thin film processing and characterization of superconducting materials. Since 2012 he has been a Research Scientist at Wolfspeed, Inc (a Cree company) in the SiC power devices R&D group. Here his research focuses on silicon carbide MOSFET processing and characterization, particularly focused on gate oxide processing and long-term device reliability. He has over 20 years of experience working with thin film processing, and materials and device characterization. Previous to his time at Wolfspeed/Cree, he has been a Visiting Professor at Florida International University in Miami, FL, and a Research Professor at North Carolina State University in the Materials Science and Engineering Department. There he had been a key investigator or PI for a variety of projects focused on functional thin film coatings. He has authored/coauthored more than 100 papers, including 2 book chapters and 10 patents.

 

Cristian Zambelli

University of Ferrara

Reliability characterization of NVM: a cross-layer approach

The reliability of non-volatile memories (NVM) is considered an important debate matter. However, most of the time such topic is addressed in sandboxes barely communicating each other: physics of failures, circuit design, system architecture, etc. When complex systems integrating multiple memory modules require to treat reliability along other features like performance and cost it is impossible to achieve a fair analysis by separating those domains. This is the case of the Solid State Drives (SSD). In this talk, we will show that by devising a cross-layer approach that embodies the knowledge of multiple aspects of a NVM (e.g., its operation modes, internal architecture, error rate, etc.) we can leverage the right tuning knobs to improve the reliability of a larger system like an SSD. The considerations derived in this talk will apply, without lack of generality, on any generation of NVM ranging from NAND Flash up to novel memory concepts.

Cristian Zambelli received the M.Sc. and the Ph.D. degrees (with honors) in electronic engineering from the University of Ferrara, Ferrara, Italy, in 2008 and 2012, respectively. Since 2015, he holds an Assistant Professor position with the same institution. His current research interests include the electrical characterization, physics, and reliability modeling of different nonvolatile memories such as NAND/NOR Flash, Phase Change Memories, Nano-MEMS memories, Resistive RAM (RRAM), and Magnetic RAM. He is also interested in the evaluation of the Solid State Drives reliability/performance trade-offs exposed by the integrated memory technology.