IIRW 2018 information to be available soon.
Training Fully Connected Networks with Non-Volatile Memories: prospects and challenges
Non-Volatile arrays of emerging memories, such as resistive memory (RRAM) or Phase-Change Memory (PCM), enable the acceleration of training and forward inference of Fully Connected (FC) Deep Neural Networks (DNNs), based on the backpropagation algorithm. However, obtained accuracies were unacceptably low due to device non-idealities. Here we show our recent work which, by introducing a novel weight structure composed of two PCMs and two 3-Transistor 1-Capacitor architectures, enables software-equivalent accuracy. Results based on real devices are provided for different datasets (MNIST, MNIST-backrand, CIFAR-10, CIFAR-100). The novel structure based on two pairs of varying significance enables accurate training, also thanks to transfer and polarity inversion techniques, thus paving the way to the development of future technology for Artificial Intelligence based on analog resistive memories.
Stefano Ambrogio obtained his PhD in 2016 in Italy, at Politecnico di Milano, under the supervision of Prof. Daniele Ielmini, working on the reliability of resistive memories and their application on neuromorphic networks. He is now working as a PostDoctoral Researcher at IBM- Research, Almaden, in the Neuromorphic Devices and Architectures Team, working on hardware accelerators based on Non-Volatile Memories for neural networks.
An Overview of Automotive Reliability
This automotive tutorial will address failure mode and mission profile specific challenges that arise from visions, trends and supply chain issues in the automotive industry. Differences in the foundry technology qualification process (incl. examples regarding tests and data assessment statistics) from a todays viewpoint towards future needs as well as interdependencies with automotive design flow elements will be discussed.
A strongly growing fraction of required semiconductor functions in upcoming vehicle architectures, as of today, is based on semiconductor technologies and IP sets that have not been designed and qualified for automotive use. The corresponding gaps between automotive application requirements and semiconductor product capabilities w.r.t. reliability, safety and security has to be analyzed and closed within the framework of a systematic, technical and economic risk management process. This process itself needs to be aligned, agreed and standardized along the supply chain. New and intense communication and work structures between car OEMs and Semiconductor vendors (IDMs, Fabless & Foundries) as well as tier one’s are needed. The mentioned process (“capability enhancement process”) covers the automotive application (i.e. ECU), the underlying hardware system (PCBA) and corresponding active and passive components from a technical as well as economic and architecture perspectives which includes system design for change management (updateability and upgradeability) - a hot topic and strongly market driven as innovation cycles continue to shrink (ADAS/AI, CCAR, Infotainment). Considering the whole vehicle live cycle cost structure, it is obvious that the technology cycle time has immense influence on change management cost efforts and re-qualification processes. A technology that is very promising from a reliability, cost and market durability standpoint is FDSOI. So, comments on the opportunities of FDSOI for automotive as well as the need for potentially new package technologies will be addressed.
Andreas Aal drives the semiconductor strategy and reliability assurance activities within the electric-/electronic development department at Volkswagen, Germany, which he joint 2011. His activities concentrate on technology capability enhancement of nodes down to 12 nm as well as optimization of power electronics for automotive applications. He is involved in two semiconductor related European projects and is a strong representative of the through-the-supply-chain-joint-development approach.
Mr. Aal has been working within the semiconductor industry since 1998 holding different positions from engineering to management working on production monitoring, process and technology development, qualification and failure analysis. He was involved in device optimization, the development of test structure design as well as new combined stress/measurement and data analysis methodologies for qualification and fWLR monitoring. He continues working in those fields, not within, but together with the semiconductor industry while the primarily focus is system reliability and optimized design flows.
Andreas (certified reliability professional) published and co-authored various papers, has given invited talks and tutorials, serves as reviewer for different Journals and has served in the technical and management committee for IEEE IIRW. He is a member of the IEEE Electron Devices, CPMT, Nuclear and Plasma Sciences, Reliability and Solid-State Circuits Societies and also a frequent participant / contributor of the JEDEC subcommittee 14.2. Since 2007 he is chair of the German ITG group 8.5.6 (VDE) on (f)WLR, reliability simulations and qualification. He is one of the founding members of the SEMI Global Automotive Advisory Council.