Fallen Leaf Lake

Tutorial Program

Andreas Kerber

Reliability Characterization of Ring Oscillator Circuits and Correlation to Discrete Device Degradation in Advanced CMOS Technology Nodes

Reliability characterization of CMOS technologies is focused on bias temperature instability (BTI), hot carrier injection (HCI) and time dependent dielectric breakdown (TDDB) using discrete n-FET and p-FET test structures. In recent years, the characterization methods for discrete devices were extended from DC to AC to better capture the widely discussed recovery effects and assess lifetime under switching conditions mimicking digital operation.

In this tutorial we will focus on reliability characterization of ring-oscillators (RO) representing a basic digital circuit. First we discuss time resolved RO frequency measurements and its importance in capturing the BTI component in digital circuit aging. Then explore identifying HCI contribution in RO by varying test temperature and using different test structure designs. We also address the relevance of self-heating in the characterization and aging of digital circuits. Finally we attempt to correlate the aging in discrete thin and thick oxide device to corresponding thin and thick oxide ROs in advanced CMOS technology nodes.

Andreas Kerber received his Diploma in physics from the University of Innsbruck, Austria, in 2001, and a PhD in electrical engineering from the TU-Darmstadt, Germany, with honors in 2004. From 1999 to 2000 he was an intern at Bell Laboratories, Lucent Technologies (Murray Hill, NJ, USA) working on the electrical characterization of ultra-thin gate oxides. From 2001 to 2003, he was the Infineon Technologies assignee to International SEMATECH at IMEC in Leuven, Belgium, where he was involved in the electrical characterization of alternative gate dielectrics for sub-100 nm CMOS technologies. From 2004 to 2006, he was with the Reliability Methodology Department at Infineon Technologies in Munich, Germany, responsible for the dielectric reliability qualification of process technology transfers of 110 and 90 nm memory products. During that time he developed a low-cost, fast wafer-level data acquisition setup for time-dependent dielectric breakdown (TDDB) testing with sub-ms time resolution. From 2006 to 2018 he was working for AMD in Yorktown Heights, NY, and GLOBALFOUNDRIES in Malta and East-Fishkill, NY, as a Principal Member of Technical Staff on front-end-of-line (FEOL) reliability research with focus on metal gate / high-k CMOS process technology, advanced transistor architecture and device-to-circuit reliability correlation. In 2018 he joined Skorpios Technologies in Albuquerque, NM, working on reliability of Si-photonic devices and currently he is exploring new opportunities in the semiconductor industry.

Dr. Kerber has contributed to more than 110 journal and conference publications and presented his work at international conferences, including the IEDM, VLSI and IRPS. In addition, he has presented tutorials on metal gate / high-k reliability characterization at the IIRW, IRPS and ICMTS. Dr. Kerber has served as a technical program committee member for the SISC, IRPS, IEDM, Infos, IIRW, ESSDERC, is a Senior Member of the IEEE and a Distinguished Lecturer (DL) for the IEEE Electron Devices Society.

Andrew Kim


BEOL (Back-End-Of-Line) Interconnect Reliability

BEOL (Back-End-Of-Line) interconnect reliability has always been a critical part of advanced semiconductor technology development and qualifications. The wear-out failure mechanisms include Electro-Migration (EM), Stress-Migration (SM), Thermal-Cycle (TC) stability, inter-/intra-metal Time-Dependent Dielectric Breakdown (TDDB), etc. This tutorial will begin with brief physical descriptions and fundamental understanding of the mechanisms with a brief explanation on some common misunderstanding on how such failure mechanisms are perceived by non-BEOL-reliability individuals during process development and manufacturing. Then, the focus of the talk will be shifted to practical aspect of explaining process-reliability interactions to provide some examples of what reliability data need to be collected and how such data can provide feedback to process development. Due to the time limit, the main focus will be about process-EM interactions and brief discussions will be made on SM and TC. Non-BEOL-reliability colleagues are strongly encouraged to attend.

Andrew Kim is a CMOS reliability R/D engineer at NSG (Non-volatile memory Solutions Group) of Intel Corporation, Folsom, CA. His current focus is BEOL reliability of Cu interconnects. He served as a chair/vice-chair of Dielectric Committee of IRPS2019/2018. Since 1998, he has been working on semiconductor interconnect reliability, BEOL process integration, eFuse design, TCAD on strained silicon, CMP modeling at various companies, gas turbine design and system reliability at General Electric. He received a B.S. with a minor in Mathematics in 1995 from California State University, Fullerton, CA, M.S. and Ph.D., respectively in 1996 and 2001, from Rensselaer Polytechnic Institute, Troy, NY, all in Mechanical Engineering.

Tian Shen


BEOL (Back‐End of Line) TDDB Reliability challenges

Back-End of Line (BEOL) Time Dependent Dielectric Breakdown (TDDB) has been one of the biggest reliability challenges for technology scaling. This tutorial will begin with the basics of TDDB and how to model it, including the physical mechanism of BEOL TDDB, typical test structures, accelerated stress conditions and voltage acceleration model for extrapolation from stress to use conditions. Failure time distribution and area scaling statistics including Weibull, and other non-Poisson statistics will also be discussed. The last part will discuss about the challenges to the BEOL TDDB with the new technology scaling, material set and integration schemes.

Tian Shen received his B.S in physics from University of Science and Technology of China, Hefei, China in 2003 and Ph.D. in physics from the Purdue University, West Lafayette, IN, USA in 2009. He was with the National Institute of Standards and Technology, Gaithersburg, MD, USA as a guest researcher from 2010 to 2012, and GLOBALFOUNDRIES from 2012 to 2018 where he worked on semiconductor MOL/BEOL reliability issues including EM, SM and TDDB from 32 to 7nm technology nodes. He is currently with IBM research at Albany, NY, as a senior reliability engineer focusing on reliability challenges with Cu interconnect, MOL and BEOL dielectrics and emerging embedded memory. He has more than 60 journals/conferences publications in the area of semiconductor devices, materials, and physics.

Adrian Chasin


Reliability challenges in advanced CMOS nodes: BTI, HCI and OSS in FinFETs and Nanowires devices

While it is proven that horizontal cylindrical Gate-All-Around (GAA) transistors can enable ultimate MOSFET scaling without the need of disruptive technology changes, the reliability aspects of such devices are still barely characterized and understood. In this work, we will describe the main reliability concerns of these novel devices, comparing their BTI performance with standard FinFETs. Moreover, instead of focusing only on specific reliability issues (e.g. BTI, hot-carrier, TDDB, etc) that are often treated separately, we also assess the degradation of stacked GAA nanowire nFETs in the full {VG,VD} bias space, which allows to identify all the degradation modes and how they interact with each other. The empirical modelling of the degradation includes various channel hot-carrier (CHC) modes as well as BTI and allows an extrapolation to 10- years lifetime in the full bias space.


Adrian Chasin is a Senior Researcher at imec - Belgium. He received the PhD in Electrical Engineering from the University of Leuven in 2014. During this time, he developed and modeled new electronic devices based on amorphous oxide-semiconductors for flexible and large-area circuits targeting RF and display applications. After working at NXP as a research scientist responsible for modelling and evaluating advanced CMOS technologies, he joined the imec reliability group in 2015. His main research interests are FEOL and MOL reliability for sub-10 CMOS technologies, with emphasis on Si, SiGe, Ge FinFETs and GAA devices. He authored and co-authored more than 60 publications.

Deepak Nayak + Amit Kale


Reliability of Hardware Systems

The reliability of a hardware system is challenging as the system level reliability depends on the reliability of its multiple modules and components. In hardware products such as smartphones, where light weight and low power requirements drive the miniaturization of its modules and components, “reliability budgeting” is required to achieve and maintain a high level of reliability of the product. Several practical examples of how this “reliability budgeting” is done will be presented. The field data from hardware system usage are collected and employed to define the reliability specs of its components. Many examples will be shown to project component reliability estimation from system level field data. Statistical analysis of field data and system level risk assessment from these data are also included. Final section presents the deployment of Machine Learning (ML) techniques to estimate the reliability of hardware systems .


Deepak Nayak - is a reliability engineer in Google Consumer Hardware Group where he leads the silicon IC reliability engineering of all hardware products, including Google Pixel phones, Google Nest products, and Pixelbooks. Before joining Google, he has worked at several semiconductor companies including Globalfoundries, Xilinx, Altera, and AMD. His work experience covers semiconductor technology research, silicon technology development and high volume manufacturing, IC design and product management, reliability and quality engineering, and advanced package technology. He is first in the world to propose and experimentally demonstrate strain-Si and strain-SiGe PMOSFETs. He holds a PhD from UCLA and an MBA from UC Berkeley and has published over 130 patents and papers in the field

of silicon technology.



Amit Kale - earned his M.S. and Ph.D. in Mechanical Engineering from the University of Florida, Gainesville in 2005. After completing his Ph.D., Amit joined General Electric Global Research Center in Niskayuna, NY and worked on research and development of jet engines and land based turbines. Amit joined Baker Hughes in 2012 and worked in the oil and gas industry for development of predictive analytics and data science for drilling equipment reliability and efficiency. Amit is currently working as a Reliability Program Leader at Google on Moonshot products. Much of Amit’s research and industry experience concerns machine learning, data science, reliability analysis and modeling, fracture and fatigue mechanics, and structural design optimization, among other topics. Amit has published over 25 publications in peer reviewed journals and conferences. He is an inventor on two patents and co‐inventor in two pending US patents in the area of data science and engineering.