Fallen Leaf Lake

Tutorial Program

Tian Shen


Back‐End of Line (BEOL) TDDB Reliability challenges

Back-End of Line (BEOL) Time Dependent Dielectric Breakdown (TDDB) has been one of the biggest reliability challenges for technology scaling. This tutorial will begin with the basics of TDDB and how to model it, including the physical mechanism of BEOL TDDB, typical test structures, accelerated stress conditions and voltage acceleration model for extrapolation from stress to use conditions. Failure time distribution and area scaling statistics including Weibull, and other non-Poisson statistics will also be discussed. The last part will discuss about the challenges to the BEOL TDDB with the new technology scaling, material set and integration schemes.

Tian Shen received his B.S in physics from University of Science and Technology of China, Hefei, China in 2003 and Ph.D. in physics from the Purdue University, West Lafayette, IN, USA in 2009. He was with the National Institute of Standards and Technology, Gaithersburg, MD, USA as a guest researcher from 2010 to 2012, and GLOBALFOUNDRIES from 2012 to 2018 where he worked on semiconductor MOL/BEOL reliability issues including EM, SM and TDDB from 32 to 7nm technology nodes. He is currently with IBM research at Albany, NY, as a senior reliability engineer focusing on reliability challenges with Cu interconnect, MOL and BEOL dielectrics and emerging embedded memory. He has more than 60 journals/conferences publications in the area of semiconductor devices, materials, and physics.


Adrian Chasin

Reliability challenges in advanced CMOS nodes: BTI, HCI and OSS in FinFETs and Nanowires devices

While it is proven that horizontal cylindrical Gate-All-Around (GAA) transistors can enable ultimate MOSFET scaling without the need of disruptive technology changes, the reliability aspects of such devices are still barely characterized and understood. In this work, we will describe the main reliability concerns of these novel devices, comparing their BTI performance with standard FinFETs. Moreover, instead of focusing only on specific reliability issues (e.g. BTI, hot-carrier, TDDB, etc) that are often treated separately, we also assess the degradation of stacked GAA nanowire nFETs in the full {VG,VD} bias space, which allows to identify all the degradation modes and how they interact with each other. The empirical modelling of the degradation includes various channel hot-carrier (CHC) modes as well as BTI and allows an extrapolation to 10- years lifetime in the full bias space.


Adrian Chasin is a Senior Researcher at imec - Belgium. He received the PhD in Electrical Engineering from the University of Leuven in 2014. During this time, he developed and modeled new electronic devices based on amorphous oxide-semiconductors for flexible and large-area circuits targeting RF and display applications. After working at NXP as a research scientist responsible for modelling and evaluating advanced CMOS technologies, he joined the imec reliability group in 2015. His main research interests are FEOL and MOL reliability for sub-10 CMOS technologies, with emphasis on Si, SiGe, Ge FinFETs and GAA devices. He authored and co-authored more than 60 publications.