Fallen Leaf Lake

Reliability Experts

Gennadi Bersuker

The Aerospace Corporation

Gennadi Bersuker focuses on the physical and electrical characterization and reliability of microelectronic devices employed in various space-related applications. Prior to joining The Aerospace Corporation, he has been a Fellow of SEMATECH working on development and characterization of advanced technology devices, in particular, scaled transistors, high-k gate stacks, non-volatile and charge trapping memories, III-V and 2D logic among other programs, with the goal to identify materials atomic/structural features affecting device electrical parameters. He is the Editor of IEEE Transactions on Device Materials and Reliability and has been involved in organizing, chairing, or serving as a committee member in a number of technical conferences, including IRPS, IEDM, APS, IRW, etc. He has published over 450 papers on the semiconductor processing and reliability and electronic properties of dielectrics.

Biju Parameshwaran


Biju Parameshwaran is currently working at Intel Corporation in the Non-volatile Solutions Group (NSG), managing a reliability team responsible for CMOS device qualification for 3D-NAND and 3D-XPoint technologies. Prior to joining Intel in 2018, Biju was at GlobalFoundries since its inception in 2009, managing the FEOL and Product Reliability teams and responsible for foundry platform technology qualification for commercial and automotive products, process co-development, aging models and reliability methodology development for advanced CMOS technology nodes (7nm/14nm/20nm HK-MG). His team also liaised with the IBM Alliance and research consortia for reliability methodology development. Prior to GlobalFoundries, he worked at AMD from 2005 to 2009 in the Logic Technology Division (LTD) working in areas of technology definition, design rule formulation, design-reliability interface, SRAM variation and reliability modeling and DFM. Biju started his professional career at Cypress Semiconductor in 1995, holding engineering and management positions in process development and transfer of a wide range of technologies like SRAMs, SONOS, SiGe-BiCMOS, and at Silicon Magnetic Systems (a subsidiary of Cypress Semiconductor) on MRAM development from 2002 to 2005. Biju holds a Bachelor of Technology (Hons.) in Metallurgical Engineering from Indian Institute of Technology (IIT), Kharagpur, India, and a M.S. in Materials Science from Arizona State University. He has co-authored 17 publications and holds 6 patents.


Chandra Mouli


Chandra Mouli is with Micron Technology Inc., Boise, ID, USA. He is currently Senior Director of Device Technology with responsibilities in the areas of advanced CMOS logic technology for memory products, device characterization, reliability analysis, compact models, test structure design, process & device modeling for all technologies under development in R&D. 


He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science (IISc), Bangalore, India and Ph.D (EE) from the University of Texas at Austin. He was with Texas Instruments for couple of years before joining UT/Austin. His interests include semiconductor devices and process technology for advanced memory, opto-electronic devices, exploratory research in the area of new materials and device structures. He has >200 issued patents and several pending in various areas of semiconductor devices and process – in advanced memory, novel devices and image sensor technology. He has served in the technical committees for various conferences, including IEDM, IRPS and SISPAD. He has also served in the review committees for NSF and SRC. He is currently an editor for IEEE Electron Device Letters (EDL).

Eduard A. Cartier


Eduard A. Cartier earned the B.E.E degree at the catholic boarding school "Collegium Maria Hilf" in Schwyz, Switzerland and the M.S and Ph.D degrees from the Swiss Federal Institute of Technology in Zurich, Switzerland. In his master thesis he studied the electronic structure of metallic glasses using high resolution X-ray photoelectron spectroscopy and inverse photoelectron spectroscopy. His Ph.D thesis reported on the electronic structure and on atomic defects in graphite intercalation compounds and in metallic glasses as measured with positron annihilation techniques. He received the silver medal of the Swiss Federal Institute of Technology for his outstanding Ph.D thesis. From 1986 to 1988 he worked at the ABB Research Center in Baden-Dattwil, Switzerland. While at ABB, his research centered around hot carrier transport in organic materials such as saturated long chain hydrocarbons and polymers and on dielectric breakdown of polymer insulators in high power applications. Since 1989, he is a research staff member of the IBM Research Division at the T.J. Watson Research Center in Yorktown Heights, NY, USA. His research activities at the T.J. Watson Research Center concentrated around hot carrier transport in silicon and silicon dioxide and around hot carrier induced oxide degradation relevant to FET in CMOS technologies and nonvolatile memory device operation and on the understanding of basic processes relevant to dielectric breakdown. Of particular interest to him was the investigation of the role played by hydrogen in the hot-carrier-induced oxide degradation processes leading to dielectric breakdown and device failure. He obtained two IBM internal awards for outstanding contributions in the field of hot carrier transport in insulators and in the field of oxide reliability predictions for electronic devices. For the last ten years, his work concentrated on the development of CMOS devices with high-k dielectrics and metal gates in the gate stack as a replacement for traditional SiO2/ploy-Si gate stacks.

Kin P. Cheung


Dr. Kin P. Cheung obtained his Ph.D. in physical chemistry from the New York University in 1983. From 83 to 2001 he worked at Bell Laboratories. From 2001 to 2006, he was an associate professor at Rutgers University. He is currently at the National Institute of Standards & Technology. Dr. Cheung published > 200 refereed journal and conference papers. He authored a book, three book chapters and edited three conference proceedings. He is an IEEE fellow and an editor of the IEEE Transaction on Device & Material Reliability. His current interests include novel memory devices, novel applications of nanoscale transistors, ultra-fast electrical measurements, and novel magnetic resonance spectroscopy.

Gerhard Rzepa

Institute for Microelectronics, TU Wien

Gerhard Rzepa received a BSc degree in Electrical Engineering in 2010 and a Diplomingenieur degree in Microelectronics in 2013, both from the TU Wien (Vienna University of Technology). In 2018 he finished his PhD studies on the topic of modeling of bias temperature instabilities at the Institute for Microelectronics, TU Wien, and obtained his doctoral degree. He continued to work at the Institute for Microelectronics as an assistant professor until the end of 2018 where he focused on the research of oxide degradation, device variability and measuring and modeling of related reliability phenomena such as bias temperature instabilities, hot carrier degradation, random telegraph noise, and stress-induced leakage currents. Starting with 2019 he joined Global TCAD Solutions GmbH as a scientist working on reliability modeling.

Hanmant Belgal


Hanmant Belgal received a B. Tech. in Electrical Engineering from the Indian Institute of Technology, Bombay (1986), and an M.S. in Electrical and Computer Engineering from the North Carolina State University, Raleigh (1990). He has worked on non-volatile memories (NVM) since 1989, starting with Xicor, then briefly at Advanced Micro Devices, before joining Intel in 1997. At Intel he is currently a Principal Engineer, managing a reliability team in the NVM Solutions Group located in Folsom, CA. In the roughly 30 years in the industry, he has worked on a dozen or so technology nodes, covering various NVM families, such as EEPROM, NOR and NAND Flash, and emerging memory technologies such as 3D XPointTM. His technical interests are mainly: to develop state-of-the-art NVM component and system technologies and products; and to gain a deeper understanding of the reliability mechanisms involved. He has published 5 papers; and 9 patents- 4 granted and 5 filed. He has been active in IRPS, having chaired or co-chaired the Memory technical committee and Workshops.


Kin-Leong Pey

Singapore University of Technology and Design (SUTD)

Kin-Leong Pey is currently the Associate Provost (Undergraduate Studies & SUTD Academy) and the Kwan Im Thong Hood Cho Temple Chair Professor in Healthcare Engineering at the Singapore University of Technology and Design (SUTD). Kin-Leong received his Bachelor of Engineering (1989) and Ph.D (1994) in Electrical Engineering from the National University of Singapore. He has held various research positions at the Institute of Microelectronics, Chartered Semiconductor Manufacturing, Agilent Technologies and National University of Singapore.


Kin-Leong is a senior member of IEEE, and a Fellow of the ASEAN Academy of Engineering & Technology and Institute of Engineer, Singapore. He was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Hsinchu, Taiwan. Kin-Leong was the Guest Editor of IEEE Transactions on Devices in and Materials Reliability in 2003-05 and 2007, and the Chair of the Singapore IEEE REL/CPMT/ED Chapter in 2004, 05 and 09. Kin Leong is currently an Editor of IEEE Transactions on Devices and Materials Reliability.


Kin-Leong has published more than 209 international refereed publications, 223 technical papers at international meetings/conferences and 6 book chapters, and holds 39 US patents. Kin-Leong has contributed significantly to the CMOS gate dielectric reliability, especially in the areas of physical analysis of ultra-thin dielectric breakdown mechanism. He was recognized in 2018 by the IEEE International Integrated Reliability Workshop as one of the top 20 experts of the Front‐End device reliability. Kin-Leong has graduated 32 PhD and more than 15 Master theses.


Luca Larcher

University of Modena and Reggio Emilia

Luca Larcher graduated in Electronic Engineering from the University of Padova, Italy, in 1998. He received his Ph.D. degree in “Information Engineering” from the University of Modena and Reggio Emilia in 2002, where is Full Professor of Electronics. Since April 1st is with Applied Materials.

His research interests include the modeling and characterization of non-volatile memory devices and of physical mechanisms governing the charge transport and degradation in high-k dielectrics, the characterization and design of integrated circuits for both communications and energy harvesting applications, and printed technology solutions for audio / automotive transducers.

He authored and co-authored one book and three book chapters, and more than 220 technical papers published on international journals and proceedings of international conferences. He has joined the technical and executive committees of the IEEE-IEDM (2006-2007, 2013-2015 – he was the chairman of the Modeling and simulation Committee in 2015), IEEE-IRPS (2011-2012, 2017-2019) and IIRW (2013-2018, he served as Technical Program Chair 2017) conferences. His H index is 41.

María Toledano Luque


María Toledano Luque works as a Member of the Technical Staff at GlobalFoundries (Malta, USA). Her main responsibility is the FEOL reliability of 12LP/12LP+ FinFET technologies. She received the Ph.D. degree in 2008 from the Universidad Complutense de Madrid (UCM, Spain). After lecturing for 3 years at the UCM, she joined the Devices Reliability and Electrical Characterization Group of imec (Belgium), in 2011. Her activities included advanced electrical characterization of charge trap vertical flash memories, and FEOL reliability/variability research of future CMOS technologies. From 2014 to 2018, she worked as a Senior/Principal Engineer in Samsung Electronics (South Korea). She was engaged in the technology definition and development of sub-7nm logic nodes. She has authored or co-authored more than 130 journal and conference papers, 3 book chapters and presented invited conference papers. She was serving as a committee member at the International Reliability Physics Symposium (IRPS) in 2013, 2014 and 2017.

Cristian Zambelli

University of Ferrara

Cristian Zambelli received the M.Sc. and the Ph.D. degrees (with honors) in electronic engineering from the University of Ferrara, Ferrara, Italy, in 2008 and 2012, respectively. Since 2015, he holds an Assistant Professor position with the same institution. His current research interests include the electrical characterization, physics, and reliability modeling of different nonvolatile memories such as NAND/NOR Flash, Phase Change Memories, Nano-MEMS memories, Resistive RAM (RRAM), and Magnetic RAM. He is also interested in the evaluation of the Solid State Drives reliability/performance trade-offs exposed by the integrated memory technology.


Barry J. O’Sullivan


Barry J. O’Sullivan received the B.Sc. degree in Applied Physics from University of Limerick, Ireland in 1998. He received the M.Eng.Sc. and Ph.D. degrees (Microelectronics), from the Tyndall Institute, Cork, Ireland, for studies characterizing defects at the silicon/dielectric interface, in 2000 and 2004, respectively. Since then, he has been at IMEC, Leuven, Belgium, initially quantifying defects and reliability of advanced gate stacks for the 45 nm and 32 nm CMOS technology nodes. From 2009-2016 he worked on high efficiency silicon solar cell design, fabrication and characterisation, while his current research focus includes reliability characterization for advanced logic and memory applications.

Subramanian S. Iyer (Subu)


Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and architectures that they may enable including in-memory analog compute. He has published over 300 papers and holds over 70 patents. He was a Master Inventor at IBM. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS as well as the treasurer of EDS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.

Thomas Kauerauf


Thomas Kauerauf received the diploma in electrical engineering from the TU Ilmenau, Ilmenau, Germany, in 2001, and the Ph.D. degree from KUL, Leuven, Belgium, in 2007. Since 2018 Thomas is a Senior Member of Technical Staff at Globalfoundries, Malta, NY, USA, serving as project lead for eNVM and 12LP+ MOL/BEOL reliability. From 2014 to 2018 he was with Samsung Electronics, Hwaseong, South Korea, working on Logic (10/7/5nm) and memory (VNAND/DRAM/MRAM) development and reliability. Prior that he was for 13 years with imec, Leuven, Belgium, in his last position as R&D Team Leader FEOL Reliability.


Tian Shen


Tian Shen received his B.S in physics from University of Science and Technology of China, Hefei, China in 2003 and Ph.D. in physics from the Purdue University, West Lafayette, IN, USA in 2009. He was with the National Institute of Standards and Technology, Gaithersburg, MD, USA as a guest researcher from 2010 to 2012, and GLOBALFOUNDRIES from 2012 to 2018 where he worked on semiconductor MOL/BEOL reliability issues including EM, SM and TDDB from 32 to 7nm technology nodes. He is currently with IBM research at Albany, NY, as a senior reliability engineer focusing on reliability challenges with Cu interconnect, MOL and BEOL dielectrics and emerging embedded memory. He has more than 60 journals/conferences publications in the area of semiconductor devices, materials, and physics.

Richard Southwick III


Richard G. Southwick, III received B.S., M.S., and Ph.D. degrees in electrical and computer engineering from Boise State University, Boise, ID, in 2004, 2008, and 2010, respectively. After completing postdoctoral research at the National Institute of Standards and Technology, Gaithersburg, MD, as a National Research Council Research Associate he joined IBM as a Research Staff Member in 2012 at the Albany Nanotech Center. At IBM, Dr. Southwick has worked on the semiconductor technology nodes of 14nm, 10nm, 7nm, and beyond 7nm technology device architectures. Recently he has focused on the reliability of STT-MRAM. Dr. Southwick has authored or co-authored over 60 journal and conference publications. Dr. Southwick has served on the organizing committee for the IEEE International Integrated Reliability Workshop from 2009–2016.

Andreas Kerber

Andreas Kerber received his Diploma in physics from the University of Innsbruck, Austria, in 2001, and a PhD in electrical engineering from the TU-Darmstadt, Germany, with honors in 2004. From 1999 to 2000 he was an intern at Bell Laboratories, Lucent Technologies (Murray Hill, NJ, USA) working on the electrical characterization of ultra-thin gate oxides. From 2001 to 2003, he was the Infineon Technologies assignee to International SEMATECH at IMEC in Leuven, Belgium, where he was involved in the electrical characterization of alternative gate dielectrics for sub-100 nm CMOS technologies. From 2004 to 2006, he was with the Reliability Methodology Department at Infineon Technologies in Munich, Germany, responsible for the dielectric reliability qualification of process technology transfers of 110 and 90 nm memory products. During that time he developed a low-cost, fast wafer-level data acquisition setup for time-dependent dielectric breakdown (TDDB) testing with sub-ms time resolution. From 2006 to 2018 he was working for AMD in Yorktown Heights, NY, and GLOBALFOUNDRIES in Malta and East-Fishkill, NY, as a Principal Member of Technical Staff on front-end-of-line (FEOL) reliability research with focus on metal gate / high-k CMOS process technology, advanced transistor architecture and device-to-circuit reliability correlation. In 2018 he joined Skorpios Technologies in Albuquerque, NM, working on reliability of Si-photonic devices and currently he is exploring new opportunities in the semiconductor industry.

Dr. Kerber has contributed to more than 110 journal and conference publications and presented his work at international conferences, including the IEDM, VLSI and IRPS. In addition, he has presented tutorials on metal gate / high-k reliability characterization at the IIRW, IRPS and ICMTS. Dr. Kerber has served as a technical program committee member for the SISC, IRPS, IEDM, Infos, IIRW, ESSDERC, is a Senior Member of the IEEE and a Distinguished Lecturer (DL) for the IEEE Electron Devices Society.

Tanya Nigam


Tanya Nigam is a Fellow at GLOBALFOUNDRIES. She obtained her PHD from KU LEUVEN in 1999 in the area of gate oxide breakdown. Since then she has worked on various challenges in the area of FEOL Reliability which include TDDB, BTI, HCI, LDMOS devices and correlation of device level reliability to product reliability. She continues to focus on device to product correlation for different failure modes in scaled technologies. She has co-authored 65+ papers in Journals and Conferences.