Alexander Shluger graduated from the Latvia State University, Riga, USSR in 1976. He received Ph.D. and Doctor of Science degrees from the L. Karpov Physics and Chemistry Research Institute, Moscow in 1981 and 1988, respectively. He joined the Royal Institution of Great Britain, London in 1991 and the faculty of the University College London in 1996, where he is a Professor of Physics from 2004. He is a Fellow of the Institute of Physics and of the American Physical Society, and a Foreign Member of the Latvian Academy of Sciences. He is a Principal Investigator at the WPI-Advanced Institute of Materials Research, Tohoku University, Japan (from 2007). His current research is focused on theoretical studies of defects in oxides and at semiconductor/oxide interfaces in conjunction with microelectronics applications, the mechanisms of photo-induced processes at oxide surfaces, as well as on modelling of imaging of insulating surfaces using Atomic Force Microscopy.
Andreas Kerber received his Diploma in physics from the University of Innsbruck, Austria, in 2001, and a PhD in electrical engineering from the TU-Darmstadt, Germany, with honors in 2014. From 1999 – 2000 he was an intern at Bell Laboratories, Lucent Technologies (Murray Hill, NJ, USA) working on the electrical characterization of ultra-thin gate oxides. From 2001 to 2003, he was the Infineon Technologies assignee to International SEMATECH at IMEC in Leuven, Belgium, where he was involved in the electrical characterization of alternative gate dielectrics for sub-100 nm CMOS technologies. From 2004 to 2006, he was with the Reliability Methodology Department at Infineon Technologies in Munich, Germany, responsible for the dielectric reliability qualification of process technology transfers of 110 and 90 nm memory products. During that time he developed a low-cost, fast wafer-level data acquisition setup for time-dependent dielectric breakdown (TDDB) testing with sub-ms time resolution. In 2006, he joined AMD in Yorktown Heights, NY, and now is with GLOBALFOUNDRIES in Malta, NY, working as a Principal Member of Technical Staff on front-end-of-line (FEOL) reliability research with focus on metal gate / high-k CMOS process technology, advanced transistor architecture and device-to-circuit reliability correlation. Dr. Kerber has contributed to more than 110 journal and conference publications and presented his work at international conferences, including the VLSI, IEDM and IRPS. In addition, he has presented tutorials on metal gate / high-k reliability characterization at the IIRW and IRPS. Dr. Kerber has served as a technical program committee member for the SISC, IRPS, IEDM, Infos, ESSDERC, is a Senior Member of the IEEE and a Distinguished Lecturer (DL) for the IEEE Electron Devices Society.
Chetan Prasad is the quality and reliability program manager for the 7nm Silicon technology node at Intel Corporation, Hillsboro, Oregon. He received his Bachelor of Engineering (B.E.) degree from the University of Mumbai, India in 1997, and his Master of Science (M.S.) and Doctor of Philosophy (Ph.D.) degrees in Electrical Engineering from Arizona State University in 1999, and 2003 respectively. Over the first 9 years of his work in the semiconductor industry, his focus was on research in transistor reliability mechanisms for Intel’s advanced process technologies, from the 90nm through the 7nm generations. In the last 6 years, his scope has broadened to encompass research on all reliability mechanisms for the entire process technology. During his tenure at Intel Corporation, he has been the recipient of 3 prestigious Intel Achievement Awards – granted to less than 0.25% of the global employee population each year – as well as over 15 divisional recognition awards. He has authored and co-authored over 60 publications and presentations in journals and conferences, including several invited talks and tutorials. His work has been awarded a U.S. Patent, with another Patent application pending. He has served on multiple Technical Program Committees during various years at IRPS, IEDM, and ESREF conferences. Over the last 8 years, he has also served as a peer reviewer for the IEEE Transactions on Electron Devices and Solid State Electronics journals. He has been recognized for his contributions to the creation of industry standards by JEDEC.
Ernest Y. Wu is a senior technical staff member at IBM Research Division and has been responsible for technology qualification and development of dielectric reliability methodologies since 1995 for many generations of CMOS technologies from 250nm down to 7nm nodes including SiO2, high-k, and low-k dielectrics across FEOL/MOL/BEOL applications with more than 150 papers, numerous invited talks and tutorials in international conferences and Journals including 15 IEDM papers as the leader author. In 2004, he received an IBM Outstanding Technical Achievement Award for the original development work on power-law acceleration model of FEOL gate dielectrics which has been widely used for technology qualification. In 2016, he received an IBM outstanding technical award for statistics and physics of transistor breakdown. He is an IEEE Fellow and his research interests include statistics, device physics and simulation, dielectric reliability physics and its applications to assessment of product/circuit failures.
Fernando Guarín is a Distinguished Member of Technical Staff at Global Foundries in East Fishkill NY. He earned his BSEE from the “Pontificia Universidad Javeriana,” in Bogotá, Colombia, the M.S.E.E. degree from the University of Arizona, and the Ph.D. in Electrical Engineering from Columbia University, NY He has been actively working in microelectronic reliability for over 37 years. From 1980 until 1988 he worked in the Military and Aerospace Operations division of National Semiconductor Corporation. In 1988 he joined IBM’s microelectronics division where he worked in the reliability physics and modeling of Advanced Bipolar, CMOS and Silicon Germanium BiCMOS technologies. He retired from IBM’s Semiconductor Research Development Center after 27 years as Senior Member of Technical Staff and joined GlobalFoundries in 2016. Dr. Guarín is an IEEE Fellow, Distinguished Lecturer for the IEEE Electron Devices Society, where he has served in many capacities including; member of the IEEE’s EDS Board of governors, chair of the EDS Education Committee, Secretary for EDS. He is the EDS President 2018-2019.
Gennadi Bersuker focuses on the physical and electrical characterization and reliability of microelectronic devices employed in various space-related applications. Prior to joining The Aerospace Corporation, he has been a Fellow of SEMATECH working on development and characterization of advanced technology devices, in particular, scaled transistors, high-k gate stacks, non-volatile and charge trapping memories, III-V and 2D logic among other programs, with the goal to identify materials atomic/structural features affecting device electrical parameters. He is the Editor of IEEE Transactions on Device Materials and Reliability and has been involved in organizing, chairing, or serving as a committee member in a number of technical conferences, including IRPS, IEDM, APS, IRW, etc. He has published over 450 papers on the semiconductor processing and reliability and electronic properties of dielectrics.
Jim Stathis received the bachelor's in physics from Washington University in St. Louis (1980), and the Ph.D. in physics from the Massachusetts Institute of Technology (1986), joining the IBM Research Division the same year. At IBM the focus of his work has been fundamental and practical studies of transistor reliability, including the electrical properties of point defects in SiO, and the role of defects in wearout and breakdown. He is the author or coauthor of more than 150 research papers and over 70 invited talks and tutorials. From November 2005 to February 2007 he served as Technical Assistant to the Vice President for Science and Technology, IBM Research Division. In February 2007 he became manager of High-k/Metal-Gate Characterization and Reliability, IBM Research. In November 2017 he became head of operations and strategy for science and technology, reporting to the Vice President of Science and Government Programs, IBM Research. Jim has served on technical program committees for IEDM, SISC, INFOS, IRPS, ESREF, IPFA, MIEL and other conferences, and as an an Associate Editor of the journal Microelectronics Reliability. He was the Technical Program Chair for IRPS 2009 and General Chair for IRPS 2011. He has presented tutorials on CMOS reliability at IRPS, ESREF, MRS, and IPFA. He is a Fellow of the American Physical Society and an IEEE Fellow.
J.W. McPherson holds a PhD degree in Physics from Florida State University. He is recognized internationally as an expert in Reliability Physics & Engineering. He has published over 200 papers on reliability, authored the Reliability Chapters for 4 Books, awarded 20 patents, and holds the title of Texas Instruments Senior Fellow Emeritus. He was a past General Chairman of the IEEE International Reliability Physics Symposium and still serves on its Board of Directors. In 2006, he was the Chairman of the International Sematech Reliability Council. Joe is an IEEE Fellow and Founder/CEO of McPherson Reliability Consulting, LLC. His semiconductor reliability expertise includes device-physics, design-in reliability, wafer-level reliability testing, and assembly-related issues. Several of the reliability models that are used today in the semiconductor industry are closely associated with his name. Most recently Dr. McPherson authored a reliability textbook that is widely used by students and practicing engineers: Reliability Physics and Engineering, Springer Publishing, 2010 with 2nd Edition appearing in 2013.
Patrick M. Lenahan is Distinguished Professor of Engineering Science and Mechanics and Co-Chair of the Inter-College Graduate Program in Materials Science and Engineering at Pennsylvania State University. He earned his B.S. degree from the University of Notre Dame and his Ph.D. from the University of Illinois at Urbana –Champaign. He did a post-doc at Princeton University. Following the post-doc, in 1980, he joined Sandia National Laboratories, Albuquerque, NM, where he served as a member of the technical staff for five years. Since 1985 he has been with Pennsylvania State University. Patrick and his students have investigated materials physics problems in systems including the interfaces of silicon and silicon carbide with silicon dioxide, hafnium oxides, silicon nitrides, and a variety of low-dielectric constant materials. The work has focused upon developing a fundamental understanding of the role of point defects in the operation of solid state electronic devices. In recent years, his group has worked to develop various electrically detected magnetic resonance techniques to explore the structure and electronic properties of point defects in fully processed devices. The work has resulted in approximately 220 journal articles, about 40 conference proceedings articles, about 300 conference presentations, and 4 patents. Patrick has been technical program chairman and general program chairman for the IEEE IIRW and has also served on the technical program committee of several other conferences including the IEEE SISC, the IEEE NSREC, the Rocky Mountain Conference on Magnetic Resonance and, for most of the last twenty years, he has served either as an invited or elected organizer of the MRS Electronic Materials Conference. He is a fellow of the IEEE.
Pey Kin Leong
Kin-Leong Pey is currently the Associate Provost (Education, SUTD Academy and Digital Learning) and a Professor at the Singapore University of Technology and Design (SUTD). Kin-Leong was appointed by the Singapore Ministry of Education to take up the current position in setting up SUTD in January 2010. He was previously the Head of the Microelectronics Division, Director of the Nanyang NanoFabrication Center and Director of the Microelectronic Centre in the School of EEE at the Nanyang Technological University. A senior member of IEEE and an IEEE Electron Devices Society Distinguished Lecturer, Kin-Leong was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Taiwan. Kin Leong is a Fellow of the ASEAN Academy of Engineering & Technology. He is an Editor of IEEE Transactions on Devices and Materials Reliability. Kin-Leong has published more than 175 international refereed publications, 185 technical papers at international meetings or conferences and 3 book chapters, and holds 38 US patents. Kin-Leong has supervised 32 PhD and more than 15 Master theses.
Souvik Mahapatra received his PhD in Electrical Engineering from IIT Bombay, Mumbai, India in 1999. During 2000-01 he was with Bell Labs, Lucent Technologies, Murray Hill, NJ, USA. Since 2002 he is with the Electrical Engineering department at IIT Bombay and presently a full professor. His research interests are CMOS scaling, reliability and memory devices. He has published over 150 papers in peer reviewed journals and conferences and delivered invited talks in major international conferences including IEEE IEDM and IRPS. He is a fellow of IEEE (Institute of Electrical and Electronics Engineers), INAE (Indian National Academy of Engineering) and IASc (Indian Academy of Sciences), and a distinguished lecturer of IEEE EDS (Electron Devices Society).
Steve Ramey manages the front-end reliability group in Intel’s Technology Development Quality and Reliability organization and has helped develop the 90nm through 7nm process technologies. He received his Ph.D. in electrical engineering from Arizona State University, M.S. in electrical engineering from University of Nevada, Las Vegas, and B.S. in Physics from Carnegie Mellon University. He has authored/coauthored more than 50 publications on reliability, device modeling, process development, metrology, and photovoltaic devices.
Stewart Rauch is currently a Principal Member of Technical Staff at GlobalFoundries, NY, working in the areas of reliability of Si photonics and RF CMOS. Formerly he was a faculty member at State University of New York, New Paltz, and a Senior Technical Staff Member at IBM Semiconductor Research and Development Center (NY), specializing in hot carrier, bias temperature instability, and soft error reliability of state of the art CMOS technologies. He is a Senior Member of IEEE, a Life Member and Distinguished Lecturer of the Electron Devices Society, and frequent journal reviewer for such publications as the IEEE Transactions on Electron Devices and the Microelectronics Reliability journals, etc.
Tanya Nigam is a Fellow at GLOBALFOUNDRIES. She obtained her PHD from KU LEUVEN in 1999 in the area of gate oxide breakdown. Since then she has worked on various challenges in the area of FEOL Reliability which include TDDB, BTI, HCI, LDMOS devices and correlation of device level reliability to product reliability. She continues to focus on device to product correlation for different failure modes in scaled technologies. She has co-authored 65+ papers in Journals and Conferences.
Tibor Grasser is an IEEE Fellow and has been the head of the Institute for Microelectronics since 2016. He has edited various books, e.g. on advanced device modeling (World Scientific), the bias temperature instability (Springer) and hot carrier degradation (Springer), is a distinguished lecturer of the IEEE EDS, is a recipient of the Best and Outstanding Paper Awards at IRPS (2008, 2010, 2012, and 2014), IPFA (2013 and 2014), ESREF (2008) and the IEEE EDS Paul Rappaport Award (2011). He currently serves as an Associate Editor for the IEEE Transactions on Electron Devices following his assignment as Associate Editor for Microelectronics Reliability (Elsevier) and has been involved in various outstanding conferences such as IEDM, IRPS, SISPAD, ESSDERC, and IIRW. Prof. Grasser's current research interests include theoretical modeling of performance aspects of 2D and 3D devices (charge trapping, reliability), starting from the ab initio level over more efficient quantum-mechanical descriptions up to TCAD modeling. The models developed in his group have been made available in the most important commercial TCAD environments.