Tutorial Program

Alexander Shluger

University College London, United Kingdom

Atomistic perspective on oxide degradation in devices

Under an applied stress bias, field-effect transistors experience gradually increasing gate leakage, noise signal, Vt shift, decrease of trans-conductance, and other degradation effects, which are usually attributed to defect generation and aggregation in the gate stacks. I will discuss how atomistic simulations of defect properties in amorphous oxide films combined with kinetic simulations of trap assisted tunnelling of electrons and ionic diffusion through oxide can provide mechanisms of oxide charging and degradation. We consider the effect of electron injection and hydrogen diffusion inside amorphous gate oxide films of SiO2, HfO2, Al2O3 and at interfaces with Si and TiN in creation of new defects, oxide degradation and dielectric breakdown. These mechanisms are used to simulate the creation and interaction of interstitial O ions with SiO2/TiN interfaces and explain the mechanisms of reset in RRAM devices.

Biography: Alexander Shluger graduated from the Latvia State University, Riga, USSR in 1976. He received Ph.D. and Doctor of Science degrees from the L. Karpov Physics and Chemistry Research Institute, Moscow in 1981 and 1988, respectively. He joined the Royal Institution of Great Britain, London in 1991 and the faculty of the University College London in 1996, where he is a Professor of Physics from 2004. He is a Fellow of the Institute of Physics and of the American Physical Society, and a Foreign Member of the Latvian Academy of Sciences. He is a Principal Investigator at the WPI-Advanced Institute of Materials Research, Tohoku University, Japan (from 2007). His current research is focused on theoretical studies of defects in oxides and at semiconductor/oxide interfaces in conjunction with microelectronics applications, the mechanisms of photo-induced processes at oxide surfaces, as well as on modelling of imaging of insulating surfaces using Atomic Force Microscopy.

Alexander Grill

imec, Belgium

Modeling and analysis of RTN in semiconductor devices

Low frequency noise or 1/f noise, closely related to random telegraph noise, is the most important noise source in modern CMOS technologies. It is caused by charge trapping of defects which modulate the drain current by randomly capturing and emitting carriers from the channel.

Low frequency noise of devices thereby is not only of interest for circuit designers but also related to different reliability phenomena like BTI, SILC or time dependent variability. This is because in nanometer scaled devices only few carriers contribute to the drain current. Thus, capturing a single charge in a defect can have a large influence on the main device parameters.

The tutorial gives an overview on the physical origins and stochastic properties of RTN. Methodologies to measure and analyze RTN signals are presented for both, the time and frequency domain. A special focus will be on robust methods for the extraction of characteristic time constants from electrical measurements and their application to extract physical defect parameters. Moreover, these methods are shown to be working in different technologies like silicon, gallium nitride, or 2D materials. To round things up, a stochastic defect-based compact model to simulate BTI, RTN and time-dependent variability on a circuit scale is presented.

Biography: Alexander Grill studied Microelectronics at the Vienna University of Technology, where he received his master’s degree in 2013 and his doctoral degree in 2018. He is currently working as a postdoctoral researcher at imec, Leuven. His main scientific interests are characterization and modeling of bias temperature instabilities and hot carrier degradation in semiconductor devices with a special focus on single defect properties. His current focus is the extraction of physical defect properties at cryogenic temperatures.

Subramanian S. Iyer

University of California, United States

Reliability challenges in advanced packaging

As CMOS scaling saturates, more and more of the onus of electronics system performance scaling has fallen on packaging giving rise to the term “advanced” packaging and heterogeneous integration. The driving force for advanced packaging is similar to CMOS scaling: lower system cost, smaller foot prints and increased performance. The method of achieving this is also similar – shrink the package and the board and increase the inter-die bandwidth and reduce inter-die latency and energy per bit transmitted. Traditional packaging has been notorious for dominating the failure pareto distribution. This stems from the complexity of packaging: solder and related brittle intermetallics, the mixing of silicon and inorganics with organic materials with their vastly different thermal and mechanical properties including coefficients of thermal expansion, and connector technology coupled with the use of larger and larger dies. Advanced packaging tends to use silicon-like processing and can be potentially less suspectable to these failure modes. However, we do expect to see different failure modes creep in. In this talk we will look at this problem from the perspective of three-dimensional integration, interposer technology, the silicon interconnect fabric as well as fan-out wafer-level packaging and flexible hybrid electronics. We argue that more integration and more intimate integration with minimal possibility for rework will make increasing use of system reliability concepts such as redundancy, smart thermal management, intelligent routing and a high degree of fault tolerance to achieve overall greater system reliability.

Finally, we point out that all reliability problems are not intrinsically bad. They just are! We will look at a couple of examples where reliability problems can be turned on their heads to solve yield and other reliability problems.

Biography: Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and device innovations that they may enable wafer-scale architectures, in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 75 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.

Brian Hoskins

NIST, United States

Foundations of emerging applications for neuromorphic networks

As Moore’s Law comes to its end and advances in computing shift the market’s demand for computing towards Artificial Intelligence, entirely new architectures, neuromorphic architectures, are coming into vogue. The different requirements of neuromorphic computers, including enormous demand for memory and a high tolerance for defects, is increasingly causing a reassessment of research priorities into nanotechnology and integrated circuit manufacturing. We will review the mathematical foundations of the most important new computing approaches in A.I. and discuss the unique ways these mathematical operations can be accelerated using nanotechnology and novel computing architectures for critical use cases, but especially for online training of neural networks as well as inference in the field where neural networks will increasingly be deployed. Looking forward, we will identify the key challenges that need to be resolved to bring emerging technologies into use as well as future trends in A.I. and computer science that may further drive research into materials science, nanotechnology, IC design, and electronic reliability.

Biography: Brian Hoskins is a Physicist in the Alternative Computing Group at the National Institute of Standards and Technology. His work primarily focuses on heterogeneous integration of emerging technologies with CMOS to improve the performance of novel computing architectures as well as novel computing approaches to exploit these new technologies. He has a B.S. and M.S. in Materials Science and Engineering from Carnegie Mellon University and a Ph.D. in Materials Science from The University of California, Santa Barbara. He was previously a National Research Council Postdoctoral Fellow at NIST.

Angelo Miele

Cisco Systems Inc., United States

Silicon photonics technology and packaging reliability and qualification testing

In recent years, the optics data communications industry has leveraged mature IC CMOS tools and processes to produce Silicon Photonics (SiPh) devices. However, unlike the IC industry where multiple end-users design circuits from a common foundry defined electrical design kit following well defined design rules, no such common PDK (Process design kit) exists to date, for Silicon Photonics. Each individual end-user / foundry designs optical circuits using their own internally designed optical components (modulator diode, capacitor, Ge PD, waveguide, coupler) and lay-out design rules. This may lead to unique situations where the CMOS foundry no longer owns the reliability obligations of the components or lay-out of design. The onus for reliability and qualification falls to the end-user, in our case Cisco.

We will present 1-Dimensional (side by side chip set with wirebond), 2-Dimensional (Chip on Chip with wirebond) and 3-Dimensional (Chip on chip with TSV) Silicon Photonics packaging design concepts and discuss how we planned our reliability/qualification testing and determined lifetime predictions of our SiPh optical components.

Biography: Angelo Miele joined Cisco Systems Inc. as part of the Lightwire Silicon Photonics acquisition in March 2012. He started his 22+ year career as a reliability engineer at JDS Uniphase. His primary role was to provide reliability support and qualification of Cisco OEM optical products including PLC and free space optics WXC ROADMS, amplifier line cards, super transport blade line cards for Cisco's 50GHz and 100GHz long haul transport solutions. He has worked as a Cisco partner for the full length of his career. He is presently the Manager of the Silicon Photonics and Transceiver Modules Reliability Group. His team is responsible for the reliability of the leading Gen 1 - CPAK Silicon Photonics transceivers, recent Gen 2 - QSFP-100G-PAM4 single lambda DR/FR and LR modules and future Gen – 3 designs for reliability. Angelo is currently leading the JEDEC Silicon Photonics Qualification and Reliability Task Group whose aim is to standardize reliability requirements across the silicon photonics eco-system within the JEDEC framework.