Reliability Experts Forum (2023)

Zakariae Chbili received the B.S. degree in electrical engineering from Sidi Mohamed Ben Abdellah University, Fes, Morocco, in 2007, the M.S. degree in electrical engineering from the Institut National des Sciences Appliquées, Toulouse, France, in 2008, and the Ph.D. degree in electrical and computer engineering from George Mason University. He was with the National Institute of Standard and Technology, Gaithersburg, MD, USA as a Guest Researcher from 2010 to 2015 and with GLOBALFOUNDRIES Inc. from 2015 to 2019 where he managed the Northeast Reliability Labs. Zak is currently with Intel Corporation Folsom CA. After managing TD CMOS Reliability for Optane memory, he is now a TD Q&R program manager ensuring successful transition of leading-edge nodes from pathfinding to development and production. His research interests include the reliability of advanced nodes, nanoribbon/GAA reliability, reliability of emerging memory devices, physics of degradation and breakdown in ultrathin gate oxides, and self-heating. Zak is a senior IEEE member and has served in several roles in the reliability community including, General Chairman of IIRW 2019, EDTM 2022 Reliability committee chair, and IRPS 2024 Gate and MOL dielectrics committee chair.

Jen-Hao Lee received the B.S. and Ph.D. degrees in material science and engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001 and 2006, respectively. He joined the Taiwan Semiconductor Manufacturing Company Limited (TSMC) since 2007 for fundamental reliability physics, including device reliability, gate oxide integrity as well as product reliability. Currently, he is taking the lead of technology qualification for TSMC's advanced process technologies.

Jeffrey Hicks is an Intel Senior Fellow and Director of Technology Reliability Pathfinding. He oversees Intel’s reliability strategy across a range of disciplines, leading programs and functions to address complex inter-disciplinary challenges spanning silicon technology, packaging, manufacturing, and product design and architecture. He is dedicated to making reliability a driving force in the advance of digital technologies through innovation within Intel and the broader ecosystem in collaboration with customers and other external partners. Mr. Hicks has worked at Intel since 1980 across a wide range of Quality and Reliability functions. He received a B.S. degree in applied physics from the California Institute of Technology, has published over two dozen technical papers and holds several patents. 

John Faricelli received his PhD in Electrical Engineering from Cornell University in 1984.

He has worked in the areas of TCAD development, MOSFET compact modeling, and interconnect modeling and reliability.

For the past nine years he has worked in the area of transistor and interconnect reliability and modeling.

He is currently a Principal Member of Technical Staff at Advanced Micro Devices in Boxborough, MA.

Bonnie E. Weir was born in Osaka, Japan. She received a B. A. in Physics from Swarthmore College in 1988 and a Ph. D. in Physics and Engineering Physics from Stevens Institute of Technology in 1993. She has explored ordered delta-doping at AT&T Bell Laboratories, soft breakdown of silicon oxynitrides at Lucent Technologies and electrostatic discharge protection at Agere Systems. She is currently a Master Engineer with Broadcom, Inc. in Allentown, Pennsylvania, where she works with designers to meet transistor-level and interconnect reliability rules while maintaining competitive design practices. With over forty publications, Weir holds 8 patents, has served on the IEDM Circuits, Reliability and Yield subcommittee and currently serves on the Reliability of Systems and Devices subcommittee. She chaired the IRPS Transistors subcommittee in 2022 and currently co-chairs the JEDEC taskgroup (142_6) on Gate Dielectric Breakdown. 

Patrick Justison received the B.S. degree in materials science from Lehigh University, Bethlehem, PA, USA, and the Ph.D. and M.S.E. degrees in materials science from The University of Texas at Austin, Austin, TX, USA. He has been with GLOBALFOUNDRIES, Malta, NY, USA, since its inception in 2009, after joining Advanced Micro Devices, Inc., Sunnyvale, CA, USA, in 2008. His focus has been primarily on BEoL reliability mechanisms and thermal mechanical wear out and CPI.  He currently leads a global reliability team, focusing on methodology development and differentiated technology offerings. 

Souvik Mahapatra received his PhD in Electrical Engineering from Indian Institute of Technology Bombay (IITB), Mumbai, India in 1999. During 2000-01 he was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA. Since 2002 he is with IITB and presently a full professor of Electrical Engineering. His research area is reliability of CMOS devices and circuits and Flash memory. He has collaborated closely with various semiconductor industries in the fab tool, EDA, IDM, foundry and fabless space. He has published more than 150 articles in peer reviewed journals and conferences, and delivered invited talks and tutorials in various IEEE conferences including IEDM and IRPS. He is a fellow of IEEE, and several Indian Engineering and Science academies (INSA, INAE and IASc).    

Erik Bury received the B.Sc., M.Sc. and PhD degrees in Electronic Engineering from the Katholieke Universiteit Leuven - Belgium, in 2009, 2011 and 2016 respectively. He is currently team leader and principal member of technical staff within the advanced reliability and robustness department of imec. His main research interests involve device self-heating effects, channel hot carrier degradation and bias temperature instabilities. He received the IPFA Best Paper award (in reliability) in 2014 and IRPS Best Paper award in 2022. He is serving or served as a technical program committee member for ESSDERC, IPFA and IRPS. 

Min-jung Jin received the B.S from the Pusan National University, S. Korea, in 2006. Upon graduation, she joined Technology Quality & Reliability of Samsung Electronics, South Korea, where she was focused on device reliability (BTI,TDDB, HCI etc) of Samsung's ten different technology generations. She worked at IBM led ISDA alliance for 20nm as Samsung assignee (2011-2013). She received the M.S from the Sungkyunkwan Univesity, S. Korea (2016-2017). Since 2017, she is responsible for SRAM and logic circuit reliability in Samsung Foundry’s advanced logic process technology.   

Miaomiao Wang received her B.S. degree in Electrical Engineering from Peking University in 2003 and furthered her education by obtaining a Ph.D. in the same field from Yale University in 2008. The same year, she embarked on her professional journey with IBM @ Albany Nanotech Center as a research staff member.  Dr. Wang is currently manager of the reliability team at IBM’s semiconductor research division. She and her team’s responsibilities revolve around advanced reliability research for present and emerging logic devices, interconnects, and memory technologies.  Dr. Wang has authored and co-authored more than 50 papers in peer reviewed journals and conferences and 30 patents. She has been invited to give several talks and tutorials on subjects related to device physics and reliability. She also served as the technical subcommittee member at numerous international conferences, including 2017 and 2018 IEEE International Electron Devices Meeting and 2017, 2022, and 2023 IEEE International Reliability Physics Symposium. Dr. Wang is a senior IEEE Member. 

Andreas Kerber received his Diploma in physics from the University of Innsbruck, Austria, in 2001, and a PhD in electrical engineering from the TU-Darmstadt, Germany, with honors in 2004. From 1999 to 2000 he was an intern at Bell Labs. From 2001 to 2003, he was the Infineon Technologies assignee to International SEMATECH at IMEC in Leuven, Belgium. From 2004 to 2006, he was with the Reliability Methodology Department at Infineon Technologies in Munich, Germany. From 2006 to 2018 he was working for AMD and GLOBALFOUNDRIES in NY as a Principal Member of Technical Staff on front-end-of-line (FEOL) reliability research with focus on metal gate / high-k CMOS process technology, advanced transistor architecture and device-to-circuit reliability correlation. From 2018 to 2019 he was with Skorpios Technologies in Albuquerque, NM, working on reliability of Si-photonic devices. From Nov. 2019 to March 2021, he was with ON-Semiconductor in Santa Clara, CA working on product quality management of CMOS image sensors. Since March 2021 he is with Intel in Santa Clara, CA working on CMOS and interconnect reliability for 3D-NAND technology.

Dr. Kerber has contributed to more than 115 journal and conference publications. He presented his work and given tutorials at various conference including VLSI, IEDM and IRPS. Dr. Kerber is a Senior Member of the IEEE and a Distinguished Lecturer (DL) for the IEEE Electron Devices Society.