4 October - 1 November 2020

All-VIRTUAL conference

Welcome to IIRW

The IEEE International Integrated Reliability Workshop (IIRW) originated from the Wafer Level Reliability Workshop in 1982. The IIRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems.

Tutorials, paper presentations, poster sessions, moderated discussion groups, special interest groups, and the informal format of the technical program provide a unique environment for understanding, developing, and sharing reliability technology and test methodologies for present and future semiconductor applications as well as ample opportunity for open discussions and interactions with colleagues.

Dear Colleagues! Dear IIRW Enthusiasts!

Unfortunately, the pandemic situation stopped us from organizing IIRW 2020 in its dedicated place, i.e. on the beautiful and beloved Fallen Leaf Lake. However, the conference will be run as a virtual event.

Despite its virtual setting, we will try to mimic the unique and relaxed atmosphere of real IIRW and implement its crucial parts (the Reliability Expert Forum, keynote talk, tutorials, and discussion groups) as sessions where the attendees can interact with the speakers, informally discuss results, and exchange ideas. We are confident that - despite all the obstacles - IIRW will be a lot of fun!

Looking forward to seeing you all on the (virtual) Lake,

Stanislav Tyaginov, General Chair IIRW 2020

(on behalf of all the management committee members)

IIRW 2020 Best student paper

"Circuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks" by Tommaso Zanotti, Francesco Maria Puglisi and Paolo Pavan

Scope

The IIRW technical program and management committee invites abstracts related to the many areas of semiconductor reliability, such as:

  • Modeling and simulation of reliability issues

    • Thermal stresses and self-heating effects (BEOL or Device)

    • Physics of failure / Device degradation effects

  • Power and wide bandgap (SiC, GaN, etc.) device reliability

  • Defect driven high volume manufacturing reliability impacts (FEOL/MOL/BEOL)

  • Gate/Interconnect dielectrics (high-k, SiO2, SiON, low-k)

  • FinFET, SOI, FDSOI, non-CMOS (III-V), and novel devices

  • Emerging technologies and devices (2D materials, IGZO, etc)

  • Transistor reliability (hot carriers, NBTI/PBTI, TDDB)

  • Conventional and emerging memory devices (RRAM, etc.)

  • Impact of transistor degradation on circuit reliability

  • Design-in reliability (products, circuits, systems, processes)

  • Customer/manufacturer product reliability requirements


Important Dates

  • Extended Deadline: July 31, 2020 → September 1, 2020

  • Author Notification: August 25, 2020 → September 15, 2020

  • Final Manuscript: October 20, 2020 → November 6, 2020

Registration fee

  • IEEE Member: $200

  • Non-IEEE Member: $250

Special Offer for Attendees: Complimentary EDS Membership

Contacts

General Chair: Stanislav Tyaginov gc.iirw@gmail.com

Technical Program Chair: Matthew Ring tpc.iirw@gmail.com

Sponsors

Patrons