Andreas Martin received his master´s degree in electronic and electrical engineering from the Technical University of Darmstadt, Germany. He worked in Tyndall Research Institute in Cork, Ireland for several years with a focus on MOS gate oxide reliability, before he started 1998 in the corporate reliability department with Infineon Technologies AG in Munich, Germany. Since then he develops methodologies for fast wafer level reliability (fWLR) monitoring and is in the lead for plasma processing induced charging damage (PID) reliability qualification for all technology nodes in-house and foundry business. He has published several papers and presented tutorials on PID characterization methodologies in recent years. Mr. Martin has served in the JEDEC 14.2 committee for over 25 years, where he currently moderates three task groups: TG142_10 on the definition of a standard for measuring and analyzing PID well charging, TG142_3 for the development of a standard on a reliability stress method for PID gate antennas and TG142_2 on the definition of a guideline on fWLR Monitoring. 

Topic: Detection and qualification of well charging originating from plasma processing induced charging damage - PID 

Devanarayanan Ettisserry earned B.E. degree in electrical engineering and M.Sc. degree in physics from Birla Institute of Technology and Science, India, in 2009. He later completed his Ph.D. in electrical engineering at the University of Maryland, College Park, USA, in 2015. Since then, he has been with Micron Technology, Boise, and has focused on ferroelectric memory technology development and reliability. Currently, he serves as a Member of Technical Staff at Micron, contributing to advanced DRAM pathfinding. His research interests include reliability physics of emerging memories and CMOS, their characterization and modeling, and process integration for next-generation DRAM.

Topic: Reliability of high-capacity Ferroelectric memories 

Souvik Mahapatra is a professor of Electrical Engineering at IIT Bombay. He works in the area of reliability of CMOS logic and flash memory devices. He interacts closely with several leading industries in IDM, fab, fabless, fab tool and EDA space. He has authored or co authored more than 200 papers in peer reviewed journals and conferences, 22 book chapters, edited 2 books, and delivered invited talks and tutorials in major IEEE conferences. He’s a fellow of IEEE and of several Indian science and engineering societies (INSA, INAE, IASc).

Topic: A Device to Circuit Aging Framework to Study NBTI Process Dependence

Dr. Tianhao Zhang is the Senior Director of R&D and the Head of the Ansys Foundry Support Team, bringing over 20 years of experience in the EDA industry. He leads the team in supporting major foundries globally, focusing on product enablement, technology development, and methodology pathfinding for Ansys products. In addition to this, he oversees ecosystem relationships and customer support. Dr. Zhang is an author of a book, has published numerous papers, and holds six US patents. He earned his Ph.D. in Electrical and Computer Engineering and an MBA from Duke University.

Topic: Innovative Thermal Solutions for 3D Heterogeneous Integration of Co-Packaged Optics

E. Perez received the M.Sc. and Ph.D. degrees in Information and Communications Technologies from the University of Valladolid (Valladolid, Spain) in 2010 and 2014, respectively. He has been with the IHP-Leibniz-Institut für innovative Mikroelektronik since 2015, where he has worked in the field of electrical characterization of RRAM devices for their implementation as Non-Volatile Memories and artificial synapses in Neuromorphic Computing applications. In 2022 he obtained the German Habilitation and the position of “Privat-Dozent” in Brandenburgische Technische Universität (BTU) Cottbus-Senftenberg.

Topic: Promises and Challenges of CMOS-Compatible RRAM Technology for In-Memory Computing Applications 

Summary: In recent decades, if there has been one electronic device that has aroused the interest of the scientific community in the field of microelectronics, it has been the memristor. In particular, RRAM technology has been considered its most promising implementation. Initially conceived to replace Flash memories as the dominant technology in non-volatile data storage, today the interest is more focused on its use to implement In-Memory Computing engines. Its simple 2-terminal structure, scalability, CMOS compatibility, low power consumption, durability and data retention make the RRAM technology an unbeatable candidate for implementing hardware accelerators of vector-matrix multiplication operations. These operations are at the heart of the computations demanded by artificial neural networks workloads and represent a huge bottleneck in conventional computing units (CPUs and GPUs) based on the von Neumann architecture. The use of RRAM technology in hardware accelerators promises the elimination of this bottleneck under the In-Memory Computing paradigm and the consequent remarkable energy savings.

Gaurav Thareja is Head of Logic and Memory Process Integration in the Metals Deposition Products division of the Semiconductor Products Group at Applied Materials, Santa Clara, USA. With a prolific career, he has made significant contributions to semiconductor device materials, process, reliability technology. He is a recognized inventor, holding 40+ US patents, having authored more than 30 publications and many invited talks. He earned his PhD in Electrical Engineering from Stanford University and has over 15 years of experience in the semiconductor industry, previously with ferroelectric technology startup for low power AI (Founding team and COO), High performance logic for 10/7/3/2nm nodes at Intel Process Technology Development (Process Integration Lead), Transistor Reliability CAD at Texas Instruments (Design engineer) and ROM circuit design (Intern) at ST Microelectronics.

Topic: Device Reliability Considerations for Logic Technology Nodes 2nm and Beyond

Roey Shaviv is a Senior Director, Engineering Management in the Metals Deposition Products division of the Semiconductor Products Group at Applied Materials, Santa Clara, USA.  He joined Applied Materials in 2012 and led the Disruptive Technology group at the Plating Business Unit.  He joined the Metal Deposition Products division in 2016 and led the Core CVD group.  In 2019 he became the Metals Lab Director.  Prior to joining Applied Materials, he was a senior Integration and Applications Technologist at Novellus Systems (now part of Lam Research), specializing in BEOL reliability and integration. Prior to this, he was the Etch Engineering Section Head, and earlier the Thin Films and CMP Engineering Section Head, at Tower Semiconductors. He was a Lecturer at the Chemistry Department of the University of Michigan and a Research Associate in the Chemistry Department of University of Illinois, Chicago.  He received a Ph.D. in Chemistry from the University of Michigan, published numerous papers and book chapters, and holds ~50 patents. 

Topic: Device Reliability Considerations for Logic Technology Nodes 2nm and Beyond