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Technical Program
Technical Program
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Keynote Speaker
Quality At Scale Beyond Silicon
Dr. Rohit Grover, Advanced Micro Devices
Biography: Rohit Grover is a semiconductor reliability leader with over 20 years of experience spanning CMOS process integration, quality and reliability engineering, early life failure modeling, and yield engineering. He currently serves as the Director of Product Quality Engineering at AMD, where he oversees pre silicon reliability assessment methodologies and early life failure rate projections for next generation products. His organization’s scope extends from silicon level defect physics through package and system level DPPM achievement, supporting both chiplet based architectures and monolithic designs.
Rohit holds a PhD and MS in Electrical and Computer Engineering from the University of Maryland and a BTech in Engineering Physics from IIT Bombay. He has authored over 50 publications, holds five patents, and co authored a Springer Verlag book on III V optical microresonators. He has also served as Chair of the IRPS Packaging & 2.5/3D Assembly Committee.
Dr. Rohit Grover
Advanced Micro Devices
Sunday Night Speaker
The Near Future of Human Spaceflight – an Astronaut Perspective
Professor Stephen Robinson, UC Davis
Biography: Stephen Robinson joined the UC Davis faculty in 2012 after a 37 year career at NASA, where he served as a machinist, lab technician, engineer, research scientist, branch chief, safety representative, and astronaut. He is now a tenured professor in Mechanical and Aerospace Engineering and Director of the UC Davis Center for Spaceflight Research.
He also leads the Human/Robotic/Vehicle Integration and Performance Lab, guiding student research in human spaceflight, spacecraft design for human health and safety, aviation safety, human automation robotic integration, human performance, control systems, and CubeSat and UAV design.
During his 17 years as an astronaut, Robinson flew four space shuttle missions, completed three spacewalks, visited the ISS twice, trained in Star City, and developed expertise in spacecraft systems, human systems integration, operational safety, robotics, aerodynamics, and fluid physics.
His honors include NASA’s Distinguished Service Medal and the UC Davis Medal. A UC Davis alumnus, he earned dual B.S. degrees in Mechanical and Aeronautical Engineering, followed by an M.S. and Ph.D. in turbulence physics from Stanford.
Professor Stephen Robinson
UC Davis
Invited Speakers
Peter Moens
onsemi Power Solutions Group, Belgium
SiO2 as a gate dielectric for SiC MOSFETs : Interface and Dielectric Lifetime
The gate dielectric of SiC MOSFETs is still considered by many to be a major reliability concern. In this talk we will discuss the state-of-the art of SiO2 as a gate dielectric for SiC power MOSFETs, both for planar and trench devices. Focus is the dielectric/semiconductor interface and on the gate dielectric long-time reliability under TDDB stress.
The electrical characterization of the interface traps is explored by uf-BTI (bias temperature instability) measurements over a wide temperature interval (-55oC+175oC) and with over 9 decades of stress and recovery time. In addition, the insights but also limitations from charge pumping to study these traps will be covered. Attempts for physical identification of the interface states through electrically detected magnetic resonance (EDMR) will be provided.
The intrinsic gate oxide reliability (under TDDB stress) and lifetime modeling is discussed including a comparison of SiC/SiO2 to Si/SiO2
Biography
Peter Moens received a Master in nuclear physics and a Ph.D. in solid state physics from the University of Gent, Belgium, in 1990 and 1993 respectively. At onsemi is working on SiC MOSFETs. He is/was a member of the technical program committees of IEDM, ISPSD, IRPS, CSMANTECH, ICSCRM, IRW, EDTM, ESSDERC and ESREF. He was the General chair of ISPSD 2012. He authored and co-authored over 200 publications in peer reviewed journals or conferences, 20 invited papers, and is the recipient of 6 best paper awards (including 2 ISPSD best paper awards as first author). He presented tutorials at IRPS, ISPSD and EDTM. He is an inductee of the ISPSD International Hall of Fame. He holds 62 US patents.
Kevin Seaton
VPT, Inc.
Designing for Reliability: Overcoming Device-Level Challenges in GaN-Based Switched Mode Power Supplies
The adoption of Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) has revolutionized switched-mode power supplies (SMPS) by enabling unprecedented efficiency and power density. However, realizing the full potential of GaN requires addressing unique device-level characteristics that depart from traditional silicon technology. This presentation explores the critical design considerations essential for developing robust and reliable GaN-based power converters.
We begin by analyzing the mechanisms behind dynamic ON-resistance (RDS(on)), detailing how charge trapping affects gate threshold voltage and on resistance. Next, we address the stringent requirements of GaN gate drives, maintaining full device enhancement with a threshold voltage that may shift with dynamic ON-resistance. Finally, the session tackles thermal management, offering practical solutions to prevent thermal runaway by examining the positive temperature coefficient of RDS(on). Participants will explore the practical challenges of GaN integration and learn how its use in SMPSs affects long-term operational reliability.
Biography
Kevin Seaton is an Advising Engineer at VPT, Inc. Holding a Master’s in Electrical Engineering from the Georgia Institute of Technology, he leverages 25 years of power electronics design experience to deliver integrated solutions for high-reliability environments. In his leadership role, Kevin strategically guides VPT's comprehensive product roadmap, spearheading technical innovation for both Space and Non-Space applications within the aerospace and defense sectors.
William Vandendaele
CEA-Leti
Reliability of FEOL devices processed at low-temperature using 3D sequential integration : overview and opportunities
This paper aims to explore the opportunities offered by 3D sequential integration and the related reliability constraints related to low temperature processing. Both digital (500°C temperature limitations) and analog devices (< 450°C) is addressed in terms of process integration and gate stack reliability (BTI, HCI). Process levers such as SPER (Solid Phase Expitaxial Regrowth), UV NLA (Nanosecond Laser Annealing) or final annealing is explored as tools to limit the process temperature in order to facilitate sequential integration while mainting reliability close to high temperature processing levels. Gate integration scheme is also investigated especially for analog I/O devices to ensure CMOS operation within the 10 years BTI limits.
Biography
William VANDENDAELE received the M.Sc. (’07) degree in nanomaterial sciences at Grenoble INP and the Ph.D. degree from University of Grenoble-Alpes (’10) in microelectronics. He joined SOITEC in 2011 where he was head of the electrical characterization of the R&D department. Between 2014 and 2023, he is in charge of the electrical characterization, tests and reliability of GaN based substrates and devices for power electronics at CEA-LETI. Since 2023, he is involved in the development of 10nm FDSOI, Low Temperature SOI and Si-Photonics technologies as a characterization and reliability expert leading a small group of engineers and students. He has authored of more than 60 papers in international conferences or journals and holds 5 patents. He has been awarded with the IEEE IRPS 2018 best paper for in-depth studies on GaN MOS-c HEMT BTI degradation. He is a former member of the RSD IEEE IEDM subcommittee and current member of the IEEE IRPS Gate/MOL subcommittee and ESREF. He has been a TPC member of IWN, GaN Marathon. He serves as regular reviewer for IEEE TED, EDL and Microelectronic Reliability.
Tutorial Speakers
Boris Butej
KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH
Trapping and Charge Transport in GaN-on-Si HEMTs: Mechanisms Behind Dynamic RDS,on and VTH Drift
Gallium nitride (GaN) offers fundamental advantages over silicon for power conversion, enabled by its wide bandgap, high critical electric field, and the polarization induced two dimensional electron gas (2DEG) with high sheet charge density. These properties translate into low specific on state resistance (RDS,on) and reduced device capacitances, making GaN high electron mobility transistors (HEMTs) highly attractive for high speed, high efficiency switching.
Under practical operating conditions, however, GaN power devices can exhibit dynamic drift phenomena - most notably increases in dynamic RDS,on and shifts in threshold voltage (VTH) - which can limit efficiency, robustness, and lifetime. This tutorial reviews the current understanding of the defect and transport driven mechanisms underlying these instabilities. Two defect classes play a central role: (i) deep states in the buffer, which are essential for vertical insulation but can enable field dependent trapping and leakage, and (ii) interface and surface related states, which modulate electron concentration in the lateral channel and contribute to transient charging. The associated trapping, detrapping, and transport processes span timescales from microseconds to kiloseconds and depend strongly on the applied operating profile, making dynamic effects challenging to predict and model.
The aim is to provide a coherent framework linking defects, charge dynamics, and operating conditions to the observed drift phenomena, offering insights for optimizing GaN HEMT design and improving reliability.
Biography
Boris Butej received the M.Sc. degree in Technical Physics from Graz University of Technology (TU Graz) in 2021 and the Ph.D. degree in Electrical Engineering from Vienna University of Technology (TU Wien) in 2026. Since 2024, he has been with KAI GmbH in Villach, a fully owned subsidiary of Infineon Technologies Austria AG, where he works as a device reliability engineer in the Device Physics group focusing on GaN power devices. His research interests include the characterization, reliability, and modeling of wide bandgap semiconductors, particularly GaN HEMTs and p GaN gate technologies. During his Ph.D., he investigated dynamic drift effects and developed a comprehensive GaN on Si buffer charging model, establishing him as a key expert in Infineon’s GaN characterization community. He has published journal and conference papers and regularly attends international conferences.
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