SiO2 as a gate dielectric for SiC MOSFETs : Interface and Dielectric Lifetime

The gate dielectric of SiC MOSFETs is still considered by many to be a major reliability concern. In this talk we will discuss the state-of-the art of SiO2 as a gate dielectric for SiC power MOSFETs, both for planar and trench devices. Focus is the dielectric/semiconductor interface and on the gate dielectric long-time reliability under TDDB stress. 

The electrical characterization of the interface traps is explored by uf-BTI (bias temperature instability) measurements over a wide temperature interval (-55oC+175oC) and with over 9 decades of stress and recovery time. In addition, the insights but also limitations from charge pumping to study these traps will be covered. Attempts for physical identification of the interface states through electrically detected magnetic resonance (EDMR) will be provided.

The intrinsic gate oxide reliability (under TDDB stress) and lifetime modeling is discussed including a comparison of SiC/SiO2 to Si/SiO2

Biography

Peter Moens received a Master in nuclear physics and a Ph.D. in solid state physics from the University of Gent, Belgium, in 1990 and 1993 respectively. At onsemi is working on SiC MOSFETs. He is/was a member of the technical program committees of IEDM, ISPSD, IRPS, CSMANTECH, ICSCRM, IRW, EDTM, ESSDERC and ESREF. He was the General chair of ISPSD 2012. He authored and co-authored over 200 publications in peer reviewed journals or conferences, 20 invited papers, and is the recipient of 6 best paper awards (including 2 ISPSD best paper awards as first author). He presented tutorials at IRPS, ISPSD and EDTM. He is an inductee of the ISPSD International Hall of Fame. He holds 62 US patents.

Designing for Reliability: Overcoming Device-Level Challenges in GaN-Based Switched Mode Power Supplies

The adoption of Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) has revolutionized switched-mode power supplies (SMPS) by enabling unprecedented efficiency and power density. However, realizing the full potential of GaN requires addressing unique device-level characteristics that depart from traditional silicon technology. This presentation explores the critical design considerations essential for developing robust and reliable GaN-based power converters.

We begin by analyzing the mechanisms behind dynamic ON-resistance (RDS(on)), detailing how charge trapping affects gate threshold voltage and on resistance.  Next, we address the stringent requirements of GaN gate drives, maintaining full device enhancement with a threshold voltage that may shift with dynamic ON-resistance. Finally, the session tackles thermal management, offering practical solutions to prevent thermal runaway by examining the positive temperature coefficient of RDS(on). Participants will explore the practical challenges of GaN integration and learn how its use in SMPSs affects long-term operational reliability.

Biography

Kevin Seaton is an Advising Engineer at VPT, Inc. Holding a Master’s in Electrical Engineering from the Georgia Institute of Technology, he leverages 25 years of power electronics design experience to deliver integrated solutions for high-reliability environments.  In his leadership role, Kevin strategically guides VPT's comprehensive product roadmap, spearheading technical innovation for both Space and Non-Space applications within the aerospace and defense sectors.

Reliability of FEOL devices processed at low-temperature using 3D sequential integration : overview and opportunities 

This paper aims to explore the opportunities offered by 3D sequential integration and the related reliability constraints related to low temperature processing. Both digital (500°C temperature limitations) and analog devices (< 450°C) is addressed in terms of process integration and gate stack reliability (BTI, HCI). Process levers such as SPER (Solid Phase Expitaxial Regrowth), UV NLA (Nanosecond Laser Annealing) or final annealing is explored as tools to limit the process temperature in order to facilitate sequential integration while mainting reliability close to high temperature processing levels. Gate integration scheme is also investigated especially for analog I/O devices to ensure CMOS operation within the 10 years BTI limits.  

Biography

William VANDENDAELE received the M.Sc. (’07) degree in nanomaterial sciences at Grenoble INP and the Ph.D. degree from University of Grenoble-Alpes (’10) in microelectronics. He joined SOITEC in 2011 where he was head of the electrical characterization of the R&D department. Between 2014 and 2023, he is in charge of the electrical characterization, tests and reliability of GaN based substrates and devices for power electronics at CEA-LETI. Since 2023, he is involved in the development of 10nm FDSOI, Low Temperature SOI and Si-Photonics technologies as a characterization and reliability expert leading a small group of engineers and students. He has authored of more than 60 papers in international conferences or journals and holds 5 patents. He has been awarded with the IEEE IRPS 2018 best paper for in-depth studies on GaN MOS-c HEMT BTI degradation. He is a former member of the RSD IEEE IEDM subcommittee and current member of the IEEE IRPS Gate/MOL subcommittee and ESREF. He has been a TPC member of IWN, GaN Marathon. He serves as regular reviewer for IEEE TED, EDL and Microelectronic Reliability.

Poly-Si Channel-Induced Time Instability of 3D NAND Flash Cell Threshold-Voltage: A Comprehensive Temperature Analysis

This work investigates the temperature (T) dependence of the threshold-voltage (VT ) instabilities in 3D NAND Flash cells arising from charge capture/emission at the grain boundaries of their polysilicon channel, linking it to the main features of current transport through the polysilicon channel under Read conditions. Experimental data are collected on both test structures and fully processed memory chips over an extended T interval going from room temperature (RT) down to 4.2 K. Results reveal a non-monotonic behavior for the magnitude of the VT instabilities with the reduction of T, with an increase appearing from RT down to about 150 K followed by a decrease entering the cryogenic regime. This turnaround is connected to the switch of the dominant electron transport mechanism across the polysilicon grain boundaries from thermionic emission to quantum-mechanical tunneling. Thanks to that, at 4.2 K polysilicon channel-induced VT instabilities do not pose a greater reliability concern for memory arrays than they do at RT.

Biography

David Gianluigi Refaldi received the M.Sc. degree (cum laude) in Engineering Physics from Politecnico di Milano in 2022, where he is currently pursuing a Ph.D. in Information Technology. Since 2022, he has been with the Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB) at Politecnico di Milano. Since 2026, he has also been with Micron Technology.

His research focuses primarily on the characterization and modeling of 3D NAND Flash memory devices operating at cryogenic temperatures for next-generation high-performance applications.

A Common Defect Picture for Hysteresis and BTI in WS₂ FETs

Two-dimensional transition-metal dichalcogenides (2D TMDs) are widely considered as possible channel materials for future logic technologies. Their practical use, however, is still strongly affected by reliability problems. In particular, pronounced hysteresis of the transfer characteristics is observed even in pristine devices, while bias temperature instability (BTI) is a mechanism leading to degradation of device performance during electrical stress. Understanding whether these two detrimental effects have a common microscopic origin is therefore important for developing predictive reliability models for TMD-based FETs.

Here, we model both hysteresis and BTI within the same physics-based framework and compare the simulations with an extensive experimental data set obtained on 300-mm-wafer-integrated dual-gate n-type WS₂ FETs. The top-gate dielectric consists of ALD-grown amorphous Al₂O₃ and HfO₂ layers. Our results indicate that hysteresis and BTI can be traced back to the same oxide defects, although different parts of the defect population may become active depending on the electrical conditions. The relevant defects include oxygen vacancies and interstitial Al in a-Al₂O₃ and oxygen vacancies and electron (bi-)polarons in a-HfO₂.

Our simulations further show that the magnitude of both degradation phenomena is governed to a large extent by the energetic position of the oxide defect bands relative to the conduction and valence bands of the semiconductor. This suggests a direct route toward improved reliability: by engineering the gate stack in such a fashion that the active defect bands are energetically separated from the semiconductor bands, both hysteresis and BTI can be strongly reduced. Therefore, these results provide a common physical picture for the two major reliability concerns in WS₂ FETs and illustrate that the misalignment between the semiconductor and trap bands is an important design knob for future 2D device technologies.

Biography

Dr. Stanislav Tyaginov received his PhD degree in physics at the Ioffe Physical-Technical Institute in 2006. Starting from 2008 he has been working at the Technical University of Vienna where he led the physics-based hot-carrier degradation model development group. For the period of 2018-2020 he was a Marie Curie postdoctoral fellow at imec, where he is currently employed as a principal researcher. Dr. Tyaginov has been serving as a technical program committee member at the IIRW (2020 general chair), IRPS, ESREF, IPFA, EDTM and has authored/co-authored more than 150 publications in peer reviewed scientific journals as well as in conference proceedings. Among them, more than 60 are journal papers. His scientific interests include HCD, BTI, TDDB, self-heating in Si, SiGe/Ge, 2D channel material based and SiC devices, as well as tunneling phenomena.

Diamond and Boron Nitride for Reliable Wide-Bandgap Electronics: From Materials Growth to Device Integration

Coming soon...

Biography

Dr. Yuji Zhao is a Professor of Electrical and Computer Engineering at Rice University, where he leads the Wide-bandgap Innovative Device Engineering (WIDE) Lab. He received his Ph.D. from the University of California, Santa Barbara in 2012 under the supervision of Nobel Laureate Professor Shuji Nakamura. His research focuses on electronic materials, advanced semiconductor devices, and nanotechnologies, with particular emphasis on diamond, boron nitride (BN), and other wide- and ultrawide-bandgap semiconductors for energy-efficient power electronics, thermal management, and quantum photonics. He has co-authored 5 book chapters, more than 290 journal papers and conference presentations, and over 20 patents. His honors include the 2019 U.S. Presidential PECASE Award, the 2023 TMS Frontiers of Materials Award, the 2019 MIT TR 35 Award, and early-career awards from NASA and the DTRA.

Reliability of High Bandwith Memories

Coming soon...

Biography

Ashish Ghai is Senior Director of HIG HBM Product and Systems Engineering at Micron Technology. He leads the global organization responsible for productizing, scaling, and enabling the successful deployment of High Bandwidth Memory (HBM) solutions across the AI and data center ecosystem. Since assuming the role in 2024, he has established and scaled an integrated, globally distributed Product and Systems Engineering organization supporting the HBM product lifecycle.

With more than 18 years of semiconductor memory experience, Ashish has held engineering and leadership roles at Micron, Western Digital, and SanDisk spanning NAND development, enterprise SSDs, product engineering, reliability, manufacturing, and system integration. He holds a master’s degree in Engineering Management and Leadership from Santa Clara University and a bachelor’s degree in Electrical Engineering from the University of Toronto.