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Keynote Speaker
Reliability Challenges & Opportunities in the AI era
Dr. Sangwoo Pae, Samsung Electronics
Biography: Sangwoo Pae received a Ph.D. in Electrical and Computer Engineering from Purdue University and worked at Intel for 13 years, followed by another 13 years at Samsung Electronics. Most recently, Sangwoo was head of Q&R, EVP for Samsung Memory business while being concurrently responsible for leading the overall Quality Synergy Project TF across Samsung DS (Device Solutions), greatly contributing to customer quality improvement and semiconductor quality process enhancements. Before working in Memory, as Q&R head & team leader, he oversaw logic process development and product quality at Samsung SLSI and Foundry, playing a key role in the successful launch of major customers' products. Some of them includes the development and qualification of 14nm and 10/8nm FinFET technologies for the mobile, HPC and Auto. At Intel, Sangwoo made significant contributions to the development of the world's first 45nm High-k Metal Gate (HKMG) process and products, while serving as a Q&R (Quality and Reliability) Program Manager then. Sangwoo has published over 120 papers and holds more than 60 patents granted and pending. He has also served on technical committees for conferences such as IRPS and IEDM. He is IEEE Sr. Member since 2008.
Dr. Sangwoo Pae
Samsung Electronics
Invited Speakers
Prof. Souvik Mahapatra
IIT Bombay
An Universal Model for CMOS Logic (BTI, SILC/TDDB, HCD) and NAND Flash Memory (P/E Cycling, DR Loss) Reliability
Reliability is a key consideration for CMOS logic and NAND flash memory devices. Logic reliability can be classified as aging - where device parameters gradually shift over time or breakdown. Bias Temperature Instability (BTI), Stress Induced Leakage Current (SILC) and Hot Carrier Degradation (HCD) are manifestations of the former, while Time Dependent Dielectric Breakdown (TDDB) is the manifestation of the latter effect. NAND flash reliability primarily concerns charge loss from a programmed level (data retention (DR) loss), which gets accelerated after repeated program/erase (P/E) cycling. In this talk, we will discuss about a generic framework of trap generation / passivation and trapping / detrapping, and tie up the seemingly diverse set of experiments by an universal underlying theory. Validation of the theory will be showcased against an extensive set of measurement data.
Biography
Souvik Mahapatra is a professor of electrical engineering at Indian Institute of Technology (IIT) Bombay, Mumbai, India. He works in the area of CMOS logic device / circuit and NAND flash memory reliability, and has close collaborations with several semiconductor industries in the IDM, fab, fabless, fab-tool and EDA space. He has published more than 200 articles in peer reviewed journals and conferences, and 22 book chapters, and has delivered invited talks and tutorials at several major international conferences. He is a fellow of IEEE and several Indian science and engineering academies (INSA, INAE and IASc). His work got recognition with a named model (Mahapatra Reliability Model) that is available in Sentaurus Device simulator from Synopsys, and is being used by the semiconductor industry.
Prof. Mario Lanza
National University of Singapore
The Neuro-Synaptic Random Access Memory (NS-RAM)
Electronic neurons and synapses are the two fundamental building blocks of next-generation artificial neural networks. Unlike
traditional computers, these systems process and store data in the same place, eliminating the need to waste time and energy
transferring data from memory to the processing unit (CPU). The problem is that implementing electronic neurons and synapses
with traditional silicon transistors requires interconnecting multiple devices—specifically, about 18 transistors per neuron and 6
per synapse. This makes them significantly larger and more expensive than a single transistor. In this talk, I will present an
ingenious way to reproduce the electronic behaviors characteristic of neurons and synapses in a single conventional silicon transistor. This discovery is revolutionary because it allows the size of electronic neurons to be reduced by a factor of 18 and that of synapses by a factor of 6. Furthermore, I will present a versatile 2-ransistors that allows switching between operating modes (neuron or synapse), without the need to dope the silicon to achieve specific substrate resistance values.
Biography
Prof. Mario Lanza is an Associate Professor of Materials Science and Engineering at the National University of Singapore, since August 2024. He got the PhD in Electronic Engineering in 2010 at the Autonomous University of Barcelona, where he won the extraordinary PhD prize. In 2010-2011 he was NSFC postdoctoral fellow at Peking University, and in 2012-2013 he was Marie Curie postdoctoral fellow at Stanford University. On September 2013 he joined Soochow University (in China), where he promoted until the rank of Full Professor. Between October 2020 and July 2024 he was full-time Associate Professor at the King Abdullah University of Science and Technology (in Saudi Arabia), where he became known for his work in the field of nano-electronics. He has published over 200 research articles in top journals like Nature, Science and Nature Electronics, many of them becoming highly cited. He has been plenary, keynote, tutorial and invited speaker in over 150 conferences, and he and his students have received some of the most prestigious awards in the world (like the IEEE Fellow). He has been often consulted by leading semiconductor companies and publishers. He is an active member of the board governors of the IEEE – Electron Devices Society, and has been involved in the technical and management committee of top conferences in the field of electron devices, including IEDM, IRPS and IPFA.
Tutorial Speakers
Dr. Fabia Farlin Athena
Stanford University
Reliability of Oxide Semiconductor Technology for Gain-Cell Embedded DRAM Applications
Oxide semiconductor (OS) technology offers significant potential for monolithic 3D integration of low-leakage, high-density embedded DRAM (eDRAM). OS FETs (such as IGZO, ITO, IWO, IO) exhibit ultra-low leakage, enabling capacitor-less DRAM cells to achieve retention times orders of magnitude longer than conventional DRAM or SRAM. However, these devices experience reliability challenges such as positive bias-temperature instability (PBTI), causing threshold voltage shifts over time. In this tutorial, I will present the reliability landscape of OS technology for two-transistor (2T) gain-cell eDRAM applications. Two primary mechanisms have been identified for PBTI: deep electron trapping and hydrogen-related defect formation. At lower temperatures under positive bias stress, electron trapping in the amorphous channel dominates. At elevated temperatures (e.g., 85 °C), hydrogen release becomes significant, creating oxygen-vacancy donors and leading to negative shifts in threshold voltage (VT), which compromise memory cell retention. Building on this understanding, I will show how optimizing the gate dielectric enhances BTI stability at high temperatures. By introducing tailored dielectric stacks, the critical temperature at which hydrogen release overtakes electron trapping can be effectively tuned, minimizing net VT shifts under stress. I will also discuss interface-dipole (ID) engineering as an independent control knob for OSFET VT, inspired from the dipole technique in silicon high-κ/metal-gate techniques . For example, inserting a positive dipole-forming oxide layer at the interface between HfO2 and OS channel can raise the VT of IWO FETs by approximately 0.45–0.50 V compared to a baseline stack. This offset remains stable from 85 °C down to cryogenic temperatures (-263.15 °C). Importantly, ID-engineered FETs demonstrate excellent reliability, exhibiting minimal VT shifts (~60 mV) under worst-case DC stress at 85 °C compared to ~300 mV for baseline devices. This orthogonal VT tuning approach has been validated across a wide variety of OS channels for instance IWO, IO, ITO, IGZO, significantly reducing leakage. Simulations indicate a reduction in refresh energy by approximately 10,000× with increased VT. Additionally, I will introduce a complementary n-p gain-cell memory, combining a p-type oxide FET (collaboration with TSMC) with an n-type oxide FET, mitigating capacitive coupling and ensuring reliable long retention. This tutorial will cover fundamentals of BTI phenomena and modeling in OS transistors, memory cell design innovations, and future outlooks. Attendees will gain insights into BTI fundamentals, recent advancements, and ongoing challenges in the practical implementation of OS gain-cell memories.
Biography
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