An Universal Model for CMOS Logic (BTI, SILC/TDDB, HCD) and NAND Flash Memory (P/E Cycling, DR Loss) Reliability

Reliability is a key consideration for CMOS logic and NAND flash memory devices. Logic reliability can be classified as aging - where device parameters gradually shift over time or breakdown. Bias Temperature Instability (BTI), Stress Induced Leakage Current (SILC) and Hot Carrier Degradation (HCD) are manifestations of the former, while Time Dependent Dielectric Breakdown (TDDB) is the manifestation of the latter effect. NAND flash reliability primarily concerns charge loss from a programmed level (data retention (DR) loss), which gets accelerated after repeated program/erase (P/E) cycling. In this talk, we will discuss about a generic framework of trap generation / passivation and trapping / detrapping, and tie up the seemingly diverse set of experiments by an universal underlying theory. Validation of the theory will be showcased against an extensive set of measurement data. 

Biography

Souvik Mahapatra is a professor of electrical engineering at Indian Institute of Technology (IIT) Bombay, Mumbai, India. He works in the area of CMOS logic device / circuit and NAND flash memory reliability, and has close collaborations with several semiconductor industries in the IDM, fab, fabless, fab-tool and EDA space. He has published more than 200 articles in peer reviewed journals and conferences, and 22 book chapters, and has delivered invited talks and tutorials at several major international conferences. He is a fellow of IEEE and several Indian science and engineering academies (INSA, INAE and IASc). His work got recognition with a named model (Mahapatra Reliability Model) that is available in Sentaurus Device simulator from Synopsys, and is being used by the semiconductor industry.

The Neuro-Synaptic Random Access Memory (NS-RAM)

Electronic neurons and synapses are the two fundamental building blocks of next-generation artificial neural networks. Unlike

traditional computers, these systems process and store data in the same place, eliminating the need to waste time and energy

transferring data from memory to the processing unit (CPU). The problem is that implementing electronic neurons and synapses

with traditional silicon transistors requires interconnecting multiple devices—specifically, about 18 transistors per neuron and 6

per synapse. This makes them significantly larger and more expensive than a single transistor. In this talk, I will present an

ingenious way to reproduce the electronic behaviors characteristic of neurons and synapses in a single conventional silicon transistor. This discovery is revolutionary because it allows the size of electronic neurons to be reduced by a factor of 18 and that of synapses by a factor of 6. Furthermore, I will present a versatile 2-ransistors that allows switching between operating modes (neuron or synapse), without the need to dope the silicon to achieve specific substrate resistance values.

Biography

Prof. Mario Lanza is an Associate Professor of Materials Science and Engineering at the National University of Singapore, since August 2024. He got the PhD in Electronic Engineering in 2010 at the Autonomous University of Barcelona, where he won the extraordinary PhD prize. In 2010-2011 he was NSFC postdoctoral fellow at Peking University, and in 2012-2013 he was Marie Curie postdoctoral fellow at Stanford University. On September 2013 he joined Soochow University (in China), where he promoted until the rank of Full Professor. Between October 2020 and July 2024 he was full-time Associate Professor at the King Abdullah University of Science and Technology (in Saudi Arabia), where he became known for his work in the field of nano-electronics. He has published over 200 research articles in top journals like Nature, Science and Nature Electronics, many of them becoming highly cited. He has been plenary, keynote, tutorial and invited speaker in over 150 conferences, and he and his students have received some of the most prestigious awards in the world (like the IEEE Fellow). He has been often consulted by leading semiconductor companies and publishers. He is an active member of the board governors of the IEEE – Electron Devices Society, and has been involved in the technical and management committee of top conferences in the field of electron devices, including IEDM, IRPS and IPFA.

Degradation mechanisms and mitigation strategies of Hafnia-based ferroelectric device reliability 

Since the discovery of ferroelectricity in HfO2-based dielectric films in 2011, ferroelectric devices using HfO2-based thin films as dielectrics have attracted strong interest. Thus, active research and developments on Si-friendly HfO2-based ferroelectric FeRAMs and FeFETs have been conducted for memory, logic and AI applications with extremely low power consumption because of the versatile properties. However, one of the strongest concerns of these ferroelectric devices is reliability. This paper introduces our recent studies on degradation mechanisms and mitigation strategies of FeRAM and FeFET reliability. For metal/ferroelectric/metal (MFM) capacitors, we discuss critical reliability issues for FeRAM applications, such as oxide breakdown, wakeup and fatigue with an emphasis on film thickness scaling. Also, for metal/ferroelectric/semiconductor (MFIS) gate stacks, we examine the complicated interaction and coupling between polarization charges, trapped charges and inversion-layer charges. Based on this knowledge, the mechanisms of memory window narrowing and read disturb of FeFETs are discussed and the mitigation technologies are addressed. 

Biography

Shinichi Takagi received B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in 1982, 1984, and 1987, respectively. He joined the Toshiba Research and Development Center, Japan, in 1987, where he was engaged in research on the device physics of Si MOSFETs. From 1993 to 1995, he was a Visiting Scholar at Stanford University, where he studied Si/SiGe hetero-structure devices. In October 2003, he moved to the University of Tokyo, where he worked as a professor in the Department of Electrical Engineering and Information Systems for 23 years. He has currently been working as a specially appointed professor in Advanced Comprehensive Research Organization, Teikyo University, Tokyo, Japan, since April 2025. His recent interests include the science and technologies of advanced CMOS, HfO2-based ferroelectric devices, and cryo-CMOS.

Investigating cryogenic behavior in irradiated FDSOI transistors: Impact of trap buildup on charge transport and electrostatic effects

In this talk I will discuss recent experiments that establish the effects of ionizing radiation on the operation of FDSOI field-effect transistors (FETs) down to cryogenic temperatures. The results elucidate the detrimental impact of total ionizing dose (TID) damage on electrostatic performance via parametric shifts in threshold voltage and subthreshold-swing, as well as on transport behavior resulting from charged-impurity scattering and its effect on field-effect mobility. The analysis is supported by theoretical modeling of quasi-ballistic devices based on Landauer transport theory relevant to the nanoscale geometries of test structures used in this study.  

Biography

Ivan Sanchez Esqueda is an assistant professor of electrical engineering at Arizona State University. His research focuses on semiconductor physics, nanotechnology, and nanoelectronics. His research contributions include the development of logic, memory, and neuromorphic devices using emerging low-dimensional materials. He has also developed device concepts for CMOS and beyond-CMOS applications and contributed to theoretical modeling/analysis of nanoscale transistors including extreme environments (cryogenic, radiation, reliability). Prof. Sanchez Esqueda is a senior member of the IEEE and serves as Associate Editor for the IEEE Transactions on Electron Devices.

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Biography

Artemisia Tsiara received her B.Sc. degree in Physics at the University of Ioannina, Greece in 2011, and her M.Sc. degree in Electrical, Electronics and Communications Engineering from Aristotle University of Thessaloniki, Thessaloniki, Greece, in 2015. In 2019, she obtained her Ph.D. degree from Université Grenoble Alpes, Grenoble, France, working in CEA-Leti on the Reliability characterization of nanowire transistors. From 2018 to 2024, she worked as a Reliability researcher on Silicon Photonics with the reliability group of imec, Leuven, focusing on exploratory & established components such as Photodetectors, Modulators, and Lasers based on Si, Ge, and III-V materials. Currently, she is in the PMO team of IC-Link as an R&D Project Leader for Silicon Photonics, supporting different bilateral customers leveraging imec's technology towards their product targets.

Thermal Effects in FDSOI Transistors at Cryogenic Temperatures

Cryogenic CMOS circuits have regained interest with the growing research toward a scalable, fault-tolerant quantum computing system. Among Si-CMOS technologies, FD-SOI ensures performance with lower power consumption at cryogenic temperatures, typically well below 100K, offering threshold voltage tunability, as well as compatibility with Si spin qubits. However, thermal effects can hinder performance gains. The low thermal conductivity of some materials at low temperature can cause severe local temperature increase, i.e. high self-heating effect, affecting the electrical performance of the device itself and its neighborhood, as well as the circuit. This work addresses thermal effects in FD-SOI transistors down to 4K, presenting experimental results on thermal resistance, spatial thermal effects, discussing their impact on performance and reliability.

Biography

Dr. Mikael Cassé received the Ph.D. degree in physics from the Institut National des Sciences Appliquées, Toulouse, France, in 2001. He studied quantum effects at low temperature in semiconductor systems. Since 2001, he is working as a Research Staff Member at CEA-Leti, Grenoble. His current research interests include DC / RF electrical characterization and modelling of advanced CMOS devices, cryoCMOS, novel CMOS device architectures and devices for quantum computing. He has been involved in several EU and French projects. He authored and co-authored more than 200 international communications in peer-reviewed journals and conference proceedings, and two book chapters.

Beyond Performance: Navigating Hardware Reliability Challenges in LLM Infrastructure

Large Language Models (LLMs) represent a significant leap in AI capabilities, yet their deployment is increasingly challenged by the reliability of the specialized hardware used for acceleration. AI training workloads demand unprecedented computational power, vast memory capacity, and robust interconnects. This talk will delve into the reliability challenges inherent in this critical hardware infrastructure. We will discuss issues pertaining to the field reliability and consistent performance of specialized AI accelerators, the integrity of memory systems, and the resilience of interconnects, all of which are becoming paramount for the stable and cost-effective operation of LLM solutions. Ensuring hardware reliability is not just an operational concern, but an escalating critical challenge for the future of scalable AI.

Biography

Dr. Preeti Chauhan is a Technical Program Manager (TPM) at Google, leading strategic and transformational initiatives in AI/ML hardware within the Data Center Quality and Reliability group. She leverages her expertise to drive improvements in data center quality, reliability, and deployment speed at Google's massive scale. Her extensive experience encompasses quality and reliability leadership for cutting-edge technologies like Intel's Foveros 3D packaging and server microprocessors. Actively engaged within the engineering community, she serves as a senior member of the Institute of Electrical and Electronics Engineers (IEEE) and co-edits the data column in the prestigious Computer magazine. Dr. Chauhan is currently serving as the 2025 Vice President for Meetings and Conferences within the IEEE Reliability Society and as a liaison to the IRPS Board of Directors.

NEO-PGA: Nonvolatile Electro-Optically Programmable Gate Array

Large-scale, electronically reconfigurable photonic integrated circuits (PICs) can enable programmable gate array (PGA) to realize extremely fast, arbitrary linear operations, with potential applications in classical and quantum optical information technology. The basic

building blocks of existing PGAs are thermally tunable broadband Mach-Zehnder-Interferometers, which pose several limitations in terms of size, power, and scalability. Chalcogenide-based phase change materials (PCMs), exhibiting large nonvolatile change in the refractive index, can potentially transform these devices, providing at least one order of magnitude reduction in the device size, zero static energy consumption, and minimal cross-talk. In this talk, I will discuss different PCMs that can be used in conjunction with silicon and silicon nitride photonics, to create reconfigurable optical switches for visible and infrared wavelengths. I will also talk about different heaters that are needed to actuate the phase transitions on-chip. Specifically, I will show how using ultrathin graphene as a heater element can provide very high energy-efficiency, close to the fundamental limit set by thermodynamics.

Biography

Prof. Arka Majumdar is a professor in the departments of Electrical and Computer Engineering and Physics at the University of Washington (UW). He is also a visiting scientist in Meta Reality Labs (2025-current). He received B. Tech. from IIT-Kharagpur (2007), where he was honored with the President’s Gold Medal. He completed his MS (2009) and Ph.D. (2012) in Electrical Engineering at Stanford University. He spent one year at the University of California, Berkeley (2012-13), and then in Intel Labs (2013-14) as postdoc before joining UW. His research interests include developing a hybrid nanophotonic platform using emerging material systems for optical information science, imaging, and microscopy. Prof. Majumdar is the recipient of multiple Young Investigator Awards from the AFOSR (2015), NSF (2019), ONR (2020) and DARPA (2021), Intel early career faculty award (2015), Amazon Catalyst Award (2016), Alfred P. Sloan fellowship (2018), UW college of engineering outstanding junior faculty award (2020), iCANX Young Scientist Award (2021), IIT-Kharagpur Young Alumni Achiever Award (2022), DARPA Director’s Award (2023), and Rising star of light award (2023). He is an Optica (2024) and SPIE (2025) fellow. He is co-founder and technical advisor of Tunoptix, a startup commercializing software defined meta-optics.