Biography: Sangwoo Pae received a Ph.D. in Electrical and Computer Engineering from Purdue University and worked at Intel for 13 years, followed by another 13 years at Samsung Electronics. Most recently, Sangwoo was head of Q&R, EVP for Samsung Memory business while being concurrently responsible for leading the overall Quality Synergy Project TF across Samsung DS (Device Solutions), greatly contributing to customer quality improvement and semiconductor quality process enhancements. Before working in Memory, as Q&R head & team leader, he oversaw logic process development and product quality at Samsung SLSI and Foundry, playing a key role in the successful launch of major customers' products. Some of them includes the development and qualification of 14nm and 10/8nm FinFET technologies for the mobile, HPC and Auto. At Intel, Sangwoo made significant contributions to the development of the world's first 45nm High-k Metal Gate (HKMG) process and products, while serving as a Q&R (Quality and Reliability) Program Manager then. Sangwoo has published over 120 papers and holds more than 60 patents granted and pending. He has also served on technical committees for conferences such as IRPS and IEDM. He is IEEE Sr. Member since 2008.