Reliability Experts Forum (2024)

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Jen-Hao Lee received the B.S. and Ph.D. degrees in material science and engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2001 and 2006, respectively. He joined the Taiwan Semiconductor Manufacturing Company Limited (TSMC) since 2007 for fundamental reliability physics, including device reliability, gate oxide integrity as well as product reliability. Currently, he is taking the lead of technology qualification for TSMC's advanced process technologies.

Yun Dai is a Group Director at Cadence Design System, where she leads Celsius Studio Product Engineering team focused on innovative Multiphysics system analysis solutions. She has built a career spanning over 20 years in chip, package and PCB power integrity, signal integrity analysis and electrical-thermal-mechanical co-analysis within the EDA sector. Yun Dai holds a bachelor’s degree in electrical engineering and a master’s degree in system engineering from Shanghai Jiao Tong University, China, and a master’s degree in general engineering from San Jose State University, California, USA. She is passionate about semiconductor technologies and innovative design strategies. 

Dr. Victor Moroz is a Synopsys Fellow, engaged in a variety of projects on modeling Design-Technology Co-Optimization, FinFETs, gate-all-around transistors, stress engineering, 3D ICs, transistor scaling, cryogenic devices, Middle-Of-Line and Back-End-Of-Line resistance and capacitance, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors, and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters, a 100+ technical papers and over 300 US and international patents. Victor has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, EDTM, and ESSDERC, including serving as a Technical Chair of SISPAD 2018 and is currently serving as an Editor of IEEE Electron Device Letters. 

Dr. Tianhao Zang is the Sr. Director of RD, the Head of Ansys foundry support team with over 20 EDA industry working experience. He leads ANSYS foundry support team to support worldwide major foundries for ANSYS products enablement, technology development, and methodology pathfinding. He is also responsible for ecosystem relationship and customer support. Dr. Zhang is the author of one book, numerous papers, and holds 5 US patents. He has a Ph.D. in Electrical and Computer Engineering and MBA from Duke University. 

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Dr. Amr Haggag is ARM silicon solutions Head of Quality. Prior he led the quality and reliability team for Google custom silicon (Tensor), technology/design reliability for Apple silicon (A-, M- and S- series) and was quality technical director at Motorola / Freescale. He has > 20 yrs semiconductor industry quality leadership experience and has served on the International Technology Roadmap for Semiconductors (ITRS) reliability committee as well as the management and technical committee of the IEEE premier conference on semiconductor reliability, IRPS. He has over 40 publications with several invited talks and tutorials in semiconductor quality and reliability including an IRPS best paper on machine learning methods to reduce field failures the data center. He received his PhD degree in 2002, his MS degree in 1999 and his BS degree in 1996 all in Electrical and Computer Engineering from the University of Illinois at Urbana Champaign.     

Dr. Donald A. Gajewski is the Director of the Device Reliability & Failure Mechanism Science group for Wolfspeed, Inc, since 2010. He currently supports silicon carbide MOSFETs, Schottky diodes, and power modules for power electronic conversion applications. He has been in the semiconductor industry reliability profession for 24 years. He completed a National Research Council Postdoctoral Research Fellowship at the National Institute of Standards and Technology, in the Semiconductor Electronics Division, in Gaithersburg, MD. He earned the Ph.D. in physics from the University of California, San Diego, partially thanks to a National Science Foundation Fellowship. He is the chair of the JEDEC JC-70 Task Group on Standards for SiC Reliability & Qualification Procedures. He serves on the technical program committees for the IRPS and ICSCRM conferences. In his spare time, he coaches soccer, basketball, and track & field for Special Olympics, North Carolina.

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Davide Tierno received the B.Sc. degree in electronic engineering from the Politecnico di Torino, Italy, in 2012, and the international joint M.Sc. degree in nanotechnologies for ICTs from Politecnico di Torino, INP Grenoble, France, and EPFL, Switzerland, in 2014. He was a visiting student at the Lawrence Berkeley National Laboratory, USA. Later he joined imec, Belgium, to pursue a Ph.D. in Materials Engineering with KU Leuven, completing it in 2019. Since 2018, he has been a Researcher in the Interconnect Performance and Reliability team at imec, focusing on understanding failure mechanisms in BEOL, MOL, and NAND devices, developing TCAD models for interconnect performance assessment, and investigating advanced metallization schemes for cryogenic applications.